Publications associées à Via traversant

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen

Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by ...

Institute of Electrical and Electronics Engineers2016

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Andreas Peter Burg, Adam Shmuel Teman, Luca Benini, Pascal Andreas Meinerzhagen

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Mohammad Amin Shokrollahi, Seyed Armin Tajalli, Christoph Walter, Ali Hormati, Anant Pratap Singh, Omid Talebi Amiri, Klaas Lammert Hofstra, Sergio Pesenti

High-speed signaling over package substrates is key to delivering the promise of 2.5D integration. Applications abound and include high-density memory interfaces, sub-division of large dies to increase yield and lower development time, sub-division of a di ...

2016

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Giovanni De Micheli, Luca Benini

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and l ...

Institute of Electrical and Electronics Engineers2015

ICCAD 2015 Contest in 3D Interlayer Cooling Optimized Network

David Atienza Alonso, Arvind Raj Mahankali Sridhar

Microchannel liquid cooling has been proposed since the late 2000s as a viable enabler for 3D integration of microprocessors to continue scaling of computing power in the face of increasingly reduced returns from CMOS technology scaling. Thermal and electr ...

ACM/IEEE Press2015

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Nico de Rooij, Danick Briand, Andres Felipe Vasquez Quintero

In this paper, a low temperature flip-chip integration technique for Si bare dies is demonstrated on flexible PET substrates with screen-printed circuits. The proposed technique is based on patterned blind vias in dry film photoresist (DP) filled with isot ...

Iop Publishing Ltd2015

Manycore Network Interfaces for In-Memory Rack-Scale Computing

Babak Falsafi, Edouard Bugnion, Boris Robert Grot, Alexandros Daglis, Stanko Novakovic

Datacenter operators rely on low-cost, high-density technologies to maximize throughput for data-intensive services with tight tail latencies. In-memory rack-scale computing is emerging as a promising paradigm in scale-out datacenters capitalizing on commo ...

2015

Microstereolithography

Philippe Renaud, Arnaud Bertsch

Microstereolithography is a 3D microfabrication technology that is fundamentally different from the techniques commonly used in cleanroom environment for the manufacturing of microelectromechanical system (MEMS) components. Most microfabrication techniques ...

Elsevier2015

Parallel vs. Serial Inter-plane communication using TSVs

Giovanni De Micheli, Yusuf Leblebici, Somayyeh Rahimian Omam

3-D integration is a promising prospect for implementing high performance multifunctional systems-on- chip. Through Silicon Vias (TSVs) are the enablers for achieving high bandwidth paths in inter-plane communications. TSVs also provide higher vertical lin ...

2014

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Via traversant

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

ICCAD 2015 Contest in 3D Interlayer Cooling Optimized Network

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Manycore Network Interfaces for In-Memory Rack-Scale Computing

Cryogenic single chip electron spin resonance detectors

Microstereolithography

Parallel vs. Serial Inter-plane communication using TSVs

Graph Chatbot

Chattez avec Graph Search

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Cryogenic single chip electron spin resonance detectors

ICCAD 2015 Contest in 3D Interlayer Cooling Optimized Network

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Microstereolithography

Parallel vs. Serial Inter-plane communication using TSVs

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

Manycore Network Interfaces for In-Memory Rack-Scale Computing

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist