Accélération (informatique)

Résumé

En architecture informatique, l'accélération (speedup en anglais) est une mesure du gain de performance entre deux systèmes traitant le même problème. Plus techniquement, c'est le gain de vitesse d'exécution d'une tâche exécutée par deux architectures similaires disposant de ressources différentes. La notion d'accélération a été établie par la loi d'Amdahl, qui se penchait principalement sur le calcul parallèle. Cependant, l'accélération peut être utilisée plus généralement pour montrer l'effet sur les performances lors de n'importe quelle amélioration des ressources. Définitions L'accélération peut être définie pour deux grandeurs différentes : la latence et le débit. La latence d'une architecture est l'inverse de la vitesse d'exécution d'une tâche : : L = \frac{1}{v} = \frac{T}{C}, où

v la vitesse d'exécution de la tâche ;
T le temps d'exécution de la tâche ;
C la charge d'exécution de la tâche. Le débit d'une architecture est le taux d'exécution d'u

Source officielle

https://fr.wikipedia.org/wiki/Acc%C3%A9l%C3%A9ration_(informatique)

À propos de ce résultat

Cette page est générée automatiquement et peut contenir des informations qui ne sont pas correctes, complètes, à jour ou pertinentes par rapport à votre recherche. Il en va de même pour toutes les autres pages de ce site. Veillez à vérifier les informations auprès des sources officielles de l'EPFL.

Publications associées (41)

Publications associées

Chargement

Personnes associées (7)

Personnes associées

Chargement

Unités associées (6)

Afficher plus

Unités associées

Chargement

Concepts associés (2)

Concepts associés

Chargement

Cours associés (2)

Cours associés

Chargement

Séances de cours associées (8)

Séances de cours associées

Chargement

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp throttling leaves several registers to be dynamically unused whenever a warp is throttled. Given the stringent cache size limitation in GPUs this work proposes a new cache management technique named Linebacker (LB) that improves GPU performance by utilizing idle register file space as victim cache space. Whenever a CTA becomes inactive, linebacker backs up the registers of the throttled CTA to the off-chip memory. Then, linebacker utilizes the corresponding register file space as victim cache space. If any load instruction finds data in the victim cache line, the data is directly copied to the destination register through a simple register-register move operation. To further improve the efficiency of victim cache linebacker allocates victim cache space only to a select few load instructions that exhibit high data locality. Through a careful design of victim cache indexing and management scheme linebacker provides 29.0% of speedup compared to the previously proposed warp throttling techniques.

ASSOC COMPUTING MACHINERY2019

Chargement

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

Giovanni Ansaloni, David Atienza Alonso, Joshua Alexander Harrison Klein, Rafael Medina Morillas, Yasir Mahmood Qureshi, Marina Zapater Sancho

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recent advances in the integration of nano-antennas, enabling novel short-distance communication paradigms, promise disruptive gains. To gauge their potential benefit for the next-generation of many-core server designs, it is crucial to explore the impact of wireless communication links from a whole-system viewpoint, considering complex architectures and applications characteristics. To this end, in this work we introduce an extension to the popular gem5 full system-level simulator, enabling the simulation of many-core platforms featuring on-chip wireless channels. This new extension allows the flexible investigation of different combinations of wireless and wired interconnects, as well as diverse connection protocols. We showcase its capabilities by performing an architectural exploration, targeting a multi-core system executing image inference using an AlexNet Neural Network benchmark. A 2.3x speedup is obtained when implementing wireless communication between cores instead of traditional on-chip wired interconnects.

2022

Chargement

TreadMarks is a distributed shared memory (DSM) system for standard Unix systems such as SunOS and Ultrix. This paper presents a performance evaluation of TreadMarks running on Ultrix using DECstation-5000/240's that are connected by a 100-Mbps switch-based ATM LAN and a 10-Mbps Ethernet. Our objective is to determine the efficiency of a user-level DSM implementation on commercially available workstations and operating systems. We achieved good speedups on the 8-processor ATM network for Jacobi (7.4), TSP (7.2), Quicksort (6.3), and ILINK (5.7). For a slightly modified version ofWater from the SPLASH benchmark suite, we achieved only moderate speedups (4.0) due to the high communication and synchronization rate. Speedups decline on the 10-Mbps Ethernet (5.5 for Jacobi, 6.5 for TSP, 4.2 for Quicksort, 5.1 for ILINK, and 2.1 for Water), re ecting the bandwidth limitations of the Ethernet. These results support the contention that, with suitable networking technology, DSM is a viable technique for parallel computation on clusters of workstations. To achieve these speedups, TreadMarks goes to great lengths to reduce the amount of communication performed to maintain memory consistency. It uses a lazy implementation of release consistency, and it allows multiple concurrent writers to modify a page, reducing the impact of false sharing. Great care was taken to minimize communication overhead. In particular, on the ATM network, we used a standard low-level protocol, AAL3/4, bypassing the TCP/IP protocol stack. Unix communication overhead, however, remains the main obstacle in the way of better performance for programs like Water. Compared to the Unix communication overhead, memory management cost (both kernel and user level) is small and wire time is negligible.

1994

Chargement