Publications associées à Processeur 64 bits

Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

Maher Kayal, Mathieu Yves Hervé Coustans, Thomas Eberhardt, Laurent Fesquet

This paper discusses the advantages of subthreshold logic for True Random Number Generators (TRNG). In this work, the entropy is modeled, and a lower bound of Shannon's entropy per output bit can quickly be estimated. Thanks to this model, sizing TRNGs in ...

IEEE2018

Massively parallel data processing for quantitative total flow imaging with optical coherence microscopy and tomography

Theo Lasser, Paul James Marchand, Daniel Pawel Szlag, Marcin Antoni Sylwestrzak

We present an application of massively parallel processing of quantitative flow measurements data acquired using spectral optical coherence microscopy (SOCM). The need for massive signal processing of these particular datasets has been a major hurdle for m ...

Elsevier2017

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Mihai Adrian Ionescu, Anna Krammer, Teodor Rosca, Josef Andreas Schuler, Wolfgang Amadeus Vitale, Cem Alper, Arnab Biswas, Emanuele Andrea Casu, Qun Zhao

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursu ...

Nature Publishing Group2017

Designing for visual appeal, simplicity and concreteness: the development and evaluation of design standards to manipulate icon characteristics

Nicolas Henchoz, Romain Simon Collaud, Andreas Sonderegger

Good icon design is now recognized as crucial in determining user experience with mobile, PC and other applications. However, research examining icon use and processing is based on the use of existing icon sets. This leaves many questions about how new ico ...

2017

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Adam Shmuel Teman, Thomas Christoph Müller, Andrea Bonetti, Jeremy Hugues-Felix Constantin, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Optimization of the Data Rate of an OOK CMOS Medical Transmitter Based on LC Oscillators

Catherine Dehollain, Kerim Türe, Gürkan Yilmaz, Franco Maloberti

This paper presents techniques for increasing communication data rates for OOK modulated signals in the case the carrier frequency is generated by a cross-coupled pair LC oscillator. The proposed circuitry completely turns off the transmitter during the tr ...

Ieee2016

Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications

Andreas Peter Burg, Adam Shmuel Teman, Georgios Karakonstantis, Shrikanth Ganapathy

Inherently error-resilient applications in areas such as signal processing, machine learning and data analytics provide opportunities for relaxing reliability requirements, and thereby reducing the overheads incurred by conventional error correction scheme ...

2015

Sound reasoning about integral data types with a reusable SMT solver interface

Viktor Kuncak, Régis William Blanc

We extend the Leon verification system for Scala with support for bit-vector reasoning, thus addressing one of its fundamental soundness limitation with respect to the treatment of integers primitives. We leverage significant progresses recently achieved i ...

ACM Press2015

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Processeur 64 bits

Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

Massively parallel data processing for quantitative total flow imaging with optical coherence microscopy and tomography

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Some Cryptanalytic Results on Lizard

Designing for visual appeal, simplicity and concreteness: the development and evaluation of design standards to manipulate icon characteristics

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Challenges and Solutions to Next-Generation Single-Photon Imagers

Optimization of the Data Rate of an OOK CMOS Medical Transmitter Based on LC Oscillators

Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications

Sound reasoning about integral data types with a reusable SMT solver interface

Graph Chatbot

Chattez avec Graph Search

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

Challenges and Solutions to Next-Generation Single-Photon Imagers

Sound reasoning about integral data types with a reusable SMT solver interface

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Massively parallel data processing for quantitative total flow imaging with optical coherence microscopy and tomography

Some Cryptanalytic Results on Lizard

Designing for visual appeal, simplicity and concreteness: the development and evaluation of design standards to manipulate icon characteristics

Optimization of the Data Rate of an OOK CMOS Medical Transmitter Based on LC Oscillators

Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications