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In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips. ...
Mining large graphs has now become an important aspect of multiple diverse applications and a number of computer systems have been proposed to provide runtime support. Recent interest in this area has led to the construction of single machine graph computa ...
Prior research demonstrates that temporal memory streaming and related address-correlating prefetchers improve performance of commercial server workloads though increased memory level parallelism. Unfortunately, these prefetchers require large on-chip meta ...
2009
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This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple ...
The challenge of wafer-scale integration of silicon nanowires into microsystems is addressed by developing a fabrication approach that utilizes a combination of Bosch-process-based nanowire fabrication with surface micromachining and chemical-mechanical-po ...
Institute of Physics2011
Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...
ASSOC COMPUTING MACHINERY2019
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The evaluation of small degree polynomials is critical for the computation of elementary functions. It has been extensively studied and is well documented. In this article, we evaluate existing methods for polynomial evaluation on superscalar architecture. ...