Concept
Clock skew
Publications associées (39)
A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications
Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne
In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis
A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022Low Noise Clock Generation: Modeling, Analysis and Implementation
The aim of this thesis is to implement, analyze and improve the selected low noise clock
generation and distribution techniques for ADC implementations. The thesis is divided into
two parts. The first part focuses on the sampling phase generation and distr ...
EPFL2021Low-Power Design of Digital VLSI Circuits around the Point of First Failure
As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...
EPFL2019