A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gates, guaranteed by the circuit architecture to be nonoverlapping and covering the totality of the sensor's exposure period. The gates can be adjusted with a temporal resolution of 17.9 ps, and the minimum measured gate width is 0.99 ns; to our knowledge, the shortest reported to date among large-format SPAD imagers. In the dual-channel mode, the burst frame rate is 49.8 and 97.7 kframes/s in the single-channel mode. A 2690-MB/s PCI express (PCIe) interface has been added to the data acquisition framework, enabling continuous operation at approximately 44 and 88 kframes/s. Due to optimizations of the gate-signal tree, we achieved a significant reduction to gate skew and gate width variation, which is negligible with respect to the SPAD temporal jitter. These improvements, along with sub-10-cps dark count rate (DCR) per pixel and 50% maximum photon detection probability (PDP), result in a sensor particularly well suited for fast acquisition fluorescence lifetime imaging microscopy (FLIM) experiments, for which we demonstrate reduced dispersion versus a single-gated sensor.

Low-Noise, High-Density Microelectronics for Multi-Mode Screening of Excitable Biological Cells

Urs Alexander Müller

In the past decades, two recording tools have established themselves as the working horses in the field of electrophysiological cell research: the microelectrode array (MEA) and the optical fluorescence imaging. The former is a grid of miniature electrodes allowing to monitor and stimulate cell networks; the latter uses voltage-sensitive dyes (VSDs) rendering the membrane potential visible. So far, researchers trying to combine these two measurement methods face complex electro-optical setups that suffer from the limitations of both techniques. On this ground, it is highly desirable to have a new tool at hand that (a) implements both measurement methods in a single device, (b) offers a high spatio-temporal resolution for both the electrical and the optical sensors, (c) is compact, (d) is easy to handle, and (e) allows long-term measurements. The project, this work is part of, aims to achieve these goals by means of a new concept: the multi-mode sensor array (MMSA). It consists of two parts: (1) a quartz-based microfabricated biointerface housing the sensing devices, i.e. platinum electrodes and amorphous silicon photodiodes; (2) an application specific integrated circuit (ASIC) for the amplification and the conditioning of the detected signals. The two devices are flip-chip bonded together by high-density indium bumps. The resulting measurement tool features a sensor array containing 1024 electrodes and 3072 photodiodes at a pitch of 60 μm and 30 μm, respectively. The main objective of this work is the development of said ASIC with the main task being the design of low-noise, high-density electronic circuits to read the signals detected by the biointerface electrodes and photodiodes. Secondary goals are the packaging of the system and the development of a data acquisition platform to visualise and analyse the measured values. In the course of this dissertation, two ASIC versions were designed: the MMSA I and MMSAII chips. With regard to the electrode low-noise amplifier (LNA), the two versions exhibit substantially different architectures. The MMSAI LNA features a fully-differential architecture, two amplification stages with selectable gain iii Abstract (60/50 dB) and a stable bandwidth of 10 kHz, and two integrated offset compensation techniques. While the measured gain and bandwidth are in good agreement with the simulations, the noise is substantially higher than anticipated since flicker noise was not taken into account in the circuit analysis. Based on the experiences from the MMSA I chip, the second ASIC was developed with a single-ended architecture with a folded-cascode amplifier at its core. It exhibits a gain of 52 dB, a bandwidth of 52 kHz, an average noise of 26 μVrms, and a power consumption of less than 85 μW. The offset compensation allows to deal with input-referred offset in a total range of 40 mV. Furthermore, each pixel was equipped with a sample & hold buffer and a programmable stimulation circuitry. The former stores the amplified signal locally thereby realising an electronic shutter for the electrode signals; the latter is centered around a SRAM (static random access memory) cell and permits the creation of complex stimulation patterns on the array. Comparing the design with literature reveals the competitiveness of the circuit in terms of noise efficiency factor versus area. For the treatment of the photodiode signals, the three-transistor active pixel sensor (APS) architecture is employed due to its simplicity and compactness. To maximise the sensitivity of the sensor, very small transistor dimensions were chosen, thereby minimising the capacitance. The measured responsivity ranges from 0.75 V/μWμs to 0.91 V/μWμs depending on the wavelenght of the incident light. The detectable amplitude can be adjusted by choosing an appropriate integration time. The developed package provides for the biocompatibility of the system, a stable casing, thermal dissipation, a container for the cell culture and nutrient solution, and modularity for easy exchange. The data acquisition platform transfers data at a rate of up to 35 MB/s to a computer via USB 2.0. Furthermore, it offers the creation of protocols to define the course of experiments including the choice of stimulation signal waveform, stimulation patterns, timing information, and recording options.

EPFL2012

Exploring information retrieval using image sparse representations

William Guicquéro

New advances in the field of image sensors (especially in CMOS technology) tend to question the conventional methods used to acquire the image. Compressive Sensing (CS) plays a major role in this, especially to unclog the Analog to Digital Converters which are generally representing the bottleneck of this type of sensors. In addition, CS eliminates traditional compression processing stages that are performed by embedded digital signal processors dedicated to this purpose. The interest is twofold because it allows both to consistently reduce the amount of data to be converted but also to suppress digital processing performed out of the sensor chip. For the moment, regarding the use of CS in image sensors, the main route of exploration as well as the intended applications aims at reducing power consumption related to these components (i.e. ADC & DSP represent 99% of the total power consumption). More broadly, the paradigm of CS allows to question or at least to extend the Nyquist-Shannon sampling theory. This thesis shows developments in the field of image sensors demonstrating that is possible to consider alternative applications linked to CS. Indeed, advances are presented in the fields of hyperspectral imaging, super-resolution, high dynamic range, high speed and non-uniform sampling. In particular, three research axes have been deepened, aiming to design proper architectures and acquisition processes with their associated reconstruction techniques taking advantage of image sparse representations. How the on-chip implementation of Compressed Sensing can relax sensor constraints, improving the acquisition characteristics (speed, dynamic range, power consumption) ? How CS can be combined with simple analysis to provide useful image features for high level applications (adding semantic information) and improve the reconstructed image quality at a certain compression ratio ? Finally, how CS can improve physical limitations (i.e. spectral sensitivity and pixel pitch) of imaging systems without a major impact neither on the sensing strategy nor on the optical elements involved ? A CMOS image sensor has been developed and manufactured during this Ph.D. to validate concepts such as the High Dynamic Range - CS. A new design approach was employed resulting in innovative solutions for pixels addressing and conversion to perform specific acquisition in a compressed mode. On the other hand, the principle of adaptive CS combined with the non-uniform sampling has been developed. Possible implementations of this type of acquisition are proposed. Finally, preliminary works are exhibited on the use of Liquid Crystal Devices to allow hyperspectral imaging combined with spatial super-resolution. The conclusion of this study can be summarized as follows: CS must now be considered as a toolbox for defining more easily compromises between the different characteristics of the sensors: integration time, converters speed, dynamic range, resolution and digital processing resources. However, if CS relaxes some material constraints at the sensor level, it is possible that the collected data are difficult to interpret and process at the decoder side, involving massive computational resources compared to so-called conventional techniques. The application field is wide, implying that for a targeted application, an accurate characterization of the constraints concerning both the sensor (encoder), but also the decoder need to be defined.

EPFL2015

Direct time-of-flight SPAD image sensors for light detection and ranging

Preethi Padmanabhan

Depth sensing is an increasingly important feature in many applications of consumer, automotive, augmented/virtual reality (AR-VR), space and bio-medical imaging. Long range, high depth resolution, high spatial resolution, and high frame rates are often conflicting requirements and difficult to be simultaneously achieved due to extreme operating conditions. Direct time-of-flight (DTOF) has evolved to becoming a powerful technique to perform light detection and ranging (LiDAR). Thanks to advances in low-jitter optical detectors, such as single-photon avalanche diodes (SPADs), and accurate chronometers like time-to-digital converters (TDCs), picosecond timing resolution is possible, thus enabling millimetric depth resolutions. High ambient light is an inevitable challenge in LiDAR applications, whose levels may exceed up to 100 klux on a bright sunny day, making it particularly challenging to detect a target submerged within an overwhelming noise floor. High ambient light operation can be accommodated by means of optical filtering, a higher laser power or temporal filtering techniques. Optical filtering is often restricted to a narrow, 10-50 nm bandwidth, insufficient at high ambient light levels. Higher laser power is not always possible, due to eye safety regulations and power constraints. Temporal filtering such as time gating and coincidence detection can thus be powerful tools to cope with high ambient light. This thesis focuses on the design of DTOF sensors for LiDAR. To that end, two SPAD-based DTOF sensors are designed. The first sensor is designed in a 3D-stacked 45/65 nm CMOS technology, thus, enabling a modular architecture where the module itself comprises of 8x16 pixels. With a 60 ps-resolution TDC at its core, the sensor provides centimetric accuracy up to 300 m range in free space. The second sensor, named Jatayu, advances the previous design by hosting 256x128 pixels, thereby, significantly improving on its spatial resolution. While retaining its modularity, Jatayu also enables multi-level coincidence detection and progressive time-gating to suppress background light. To the best of the authorâs knowledge, progressive gating has been implemented in a LiDAR for the first time in this thesis. Designed in a 3D-stacked 45/22 nm CMOS technology, the sensor achieves under 7 cm accuracy over 100 m ranging and 10 klux background light. With its capability of acquiring 128Â£128, 3D depth maps of high dynamic range scenes, Jatayu is highly suitable for a variety of imaging applications in many different scenarios.

EPFL2021