Publications associées à Mémoire morte

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi

The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

2024

How to Achieve Large-Area Ultra-Fast Operation of MoS 2 Monolayer Flash Memories?

Aleksandra Radenovic, Andras Kis, Mukesh Kumar Tripathi, Zhenyu Wang, Asmund Kjellegaard Ottesen, Yanfei Zhao, Guilherme Migliato Marega, Hyungoo Ji

Memory devices have returned to the spotlight due to increasing interest in using in-memory computing architectures to make data-driven algorithms more energy-efficient. One of the main advantages of this architecture is the efficient performance of vector ...

2023

Ferroelectric Junctionless Double-Gate Silicon-On-Insulator FET as a Tripartite Synapse

Mihai Adrian Ionescu, Igor Stolichnov, Ali Saeidi, Sadegh Kamaei Bahmaei, Matteo Cavalieri, Carlotta Gastaldi

In this work, we report the concept and experimentally demonstrate the first tunable ferroelectric (Fe) junctionless (JL) transistor (Fe-JLFET), capable of emulating the functionality of biological tri-partite synapses, which is an artificial three-termina ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Tuning paradigm of external stimuli driven electronic, optical and magnetic properties in hybrid perovskites and metalorganic complexes br

Mohammad Khaja Nazeeruddin

We have witnessed a wide range of theoretical as well as experimental investigations to envisage external stimuli induced changes in electronic, optical and magnetic properties in the metal organiccomplexes, while hybrid perovskites have recently joined th ...

ELSEVIER SCI LTD2022

Design for Test With Unreliable Memories by Restoring the Beauty of Randomness

Andreas Peter Burg, Reza Ghanaatian Jahromi, Marco Widmer

This article presents a design-for-test methodology for embedded memories. The methodology relies on a fully random fault model of post-fabrication errors, which results in a low-overhead test strategy. The methodology's effectiveness is demonstrated on an ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Model order reduction for compressible flows solved using the discontinuous Galerkin methods

Jan Sickmann Hesthaven

Projection-based reduced order models (ROM) based on the weak form and the strong form of the discontinuous Galerkin (DG) method are proposed and compared for shock-dominated problems. The incorporation of dissipation components of DG in a consistent manne ...

ACADEMIC PRESS INC ELSEVIER SCIENCE2022

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS2

Andras Kis, Guilherme Migliato Marega

Two-dimensional materials (2DMs) have found potential applications in many areas of electronics, such as sensing, memory systems, optoelectronics, and power. Despite an intense experimental work, the literature is lacking of accurate modeling of nonvolatil ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Andreas Peter Burg, Reza Ghanaatian Jahromi

A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomi ...

2022

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Mémoire morte

Secure Interface Design Leveraging Hardware/Software Support

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

How to Achieve Large-Area Ultra-Fast Operation of MoS 2 Monolayer Flash Memories?

Ferroelectric Junctionless Double-Gate Silicon-On-Insulator FET as a Tripartite Synapse

Tuning paradigm of external stimuli driven electronic, optical and magnetic properties in hybrid perovskites and metalorganic complexes br

Design for Test With Unreliable Memories by Restoring the Beauty of Randomness

STEPS 4.0: Fast and memory-efficient molecular simulations of neurons at the nanoscale

Model order reduction for compressible flows solved using the discontinuous Galerkin methods

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS2

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Graph Chatbot

Chattez avec Graph Search

Model order reduction for compressible flows solved using the discontinuous Galerkin methods

Ferroelectric Junctionless Double-Gate Silicon-On-Insulator FET as a Tripartite Synapse

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS2

Design for Test With Unreliable Memories by Restoring the Beauty of Randomness

STEPS 4.0: Fast and memory-efficient molecular simulations of neurons at the nanoscale