Microélectronique | EPFL Graph Search

vignette|Circuit intégré logique La microélectronique est une spécialité du domaine de l'électronique qui s'intéresse à l'étude et à la fabrication de composants électroniques à l'échelle micrométrique. Ces composants sont fabriqués à partir de matériaux semi-conducteurs (comme le silicium) au moyen de diverses technologies dont la photolithographie. Cette technologie permet l'intégration de nombreuses fonctions électroniques sur un même morceau de silicium (ou autre semi-conducteur) et donc à un coût de fabrication moins élevé. Les circuits ainsi réalisés sont appelés puces ou circuits intégrés. Ils peuvent être standards ou spécifiques à une application (ils sont alors nommés ASIC : application-specific integrated circuit). Tous les composants électroniques discrets : les transistors, les condensateurs, les inductances, les résistances, les diodes et les isolants et les conducteurs ont leur équivalent en microélectronique. Description Les circuits intégrés numériques son

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device performance. As the density of number of devices increases a rise in dynamic and especially static power dissipation is ever more present, making this the biggest issue in microelectronics today. Planar silicon devices are therefore already being replaced by multiple-gate architectures and will be replaced by new channel materials and new switching mechanisms during the next 10 years. A means to decrease the threshold and supply voltage and, therefore minimizing power dissipation, is to employ devices which exhibit a steeper slope than the MOSFET limit of 60 mV/dec at room temperature. The Tunnel FET promises steep turn-on characteristics and low leakage currents as compared to MOSFETs which make it attractive for low-power operation. A great deal of work over the past years has been done to boost device performance of Tunnel FETs by combining ultimate wrap-gate architectures, incorporation of III/V materials and band engineering for hetero-tunnel junctions. The latter is seen as an ideal route towards achieving high drive currents and steep sub-threshold slopes at low supply voltages. This thesis investigates both Si Tunnel FETs and the route towards heterostructure Tunnel FETs, but also the technological challenges to achieve these device structures. The first part of this work deals with vapor-liquid-solid grown silicon in-situ doped n+-i-p nanowire Tunnel FETs in a lateral geometry, where the influence of the gate dielectric, i.e., SiO2 or HfO2, on device performance is investigated along with the study of low-temperature behavior. The devices having the strongest gate coupling due to the high-κ gate oxide HfO2 are shown to exhibit the best device performance as compared with the SiO2 gate stack. A vertical process for Si FETs is developed and improved to obtain a fully wrap-gate geometry. It is adaptable to different material systems and is the basis for the ongoing work on InAs-on-Si nanowire Tunnel FETs. Improved performance for these heterostructure devices requires in particular high doping concentrations as well as abrupt doping profiles to achieve high tunnel currents. Therefore, the second part focuses on the InAs material system and specifically the study of dopant incorporation. Doping is done in-situ using different precursors during growth. The InAs nanowires are grown in SiO2 mask openings on 〈111〉 Si substrates in a metal-organic vapor phase epitaxy process. The effect of the dopants and growth parameters on radial and vertical growth rates, wire morphology and resistivity is investigated. A method utilizing the measured Seebeck coefficient of the InAs nanowires to extract doping densities without the need of assuming a mobility value is presented. Two other reference methods where I-V characteristics of homo-and heterojunction InAs tunnel diodes are fitted by TCAD simulations confirm this approach. Doping densities ranging from 1·1017 cm−3 to 7.1·1019 cm−3 were achieved which is comparable to the highest doping concentration reported in bulk InAs. Furthermore, single vertical pn+-junctions are fabricated by growing n-type InAs nanowires on p-type InAs substrates, which show high tunnel current densities of 500 kA/cm2 at 0.3 V reverse bias. In the forward direction, negative differential resistance is obtained below 200 K, which is the characteristic feature of an Esaki diode.

EPFL2012

A new versatile hybrid MEMS technology for high sensitivity, fluid proof sensing applications.

Matthias Neuenschwander

The field of micro electromechanical systems (MEMS) evolved from the microelectronic industry and the technologies developed to fabricate integrated circuits. As a result, MEMS are commonly fabricated on silicon wafers. The development of MEMS has been driven by three main merits: miniaturisation, microelectronics integration, and parallel fabrication with high precision. Many operational properties scale well with smaller sizes. In addition, integrated electronic circuitry allows embedding MEMS with computing or networking capabilities, while parallel manufacturing enables the fabrication of many identical devices on a single wafer, reducing the unit cost. The main MEMS application is transducers which transform signals from one form of energy to another, and can be used for perception (sensors) or to produce actions (actuators). Silicon and other microelectronic materials like metals have enabled very high-performance MEMS transducers because these materials can be used for a range of very effective actuating and sensing principles.More recently, polymers have started to be used in MEMS because of their unique electrical, physical and chemical properties which include biocompatibility, viscoelasticity and mechanical shock tolerance. They are also much softer than silicon or metals, and they can be processed using many techniques that allow unique low-cost, batch-style fabrication and packaging. However, polymers have relatively low glass-transition and melting temperatures. As a result, the advantages of polymers cannot easily be combined with high-performance actuating and sensing elements as these are based on silicon technology and require high-temperature fabrication steps. Here, a hybrid-MEMS fabrication process is used to address this issue. The developed devices are based on a trilayer structure, where a thick polymer core is sandwiched between two hard thin films, while electronic layers are embedded within in a fluid-compatible way.The objective of this thesis is to turn hybrid-MEMS into a benchmark MEMS technology. This involves many different aspects. First, sensing and actuation elements are integrated into trilayer devices, and their performance is analysed. Then, some more unique possibilities offered by hybrid-MEMS are exploited. A way to fabricate electronics on multiple layers is developed, which allows different electronic features to be integrated in parallel. In addition, three-dimensional bulk features fabricated at several levels are demonstrated. This is possible because the hybrid-MEMS process is based on the bonding of multiple wafers.All these new fabrication features are demonstrated in atomic force microscopy (AFM) applications. Self-actuated trilayer AFM cantilevers with sharp silicon tips are used to boost imaging speeds in the off-resonance tapping (ORT) mode, thanks to an order of magnitude faster surface probing rates. Furthermore, fully integrated ORT imaging is demonstrated with self-actuated piezoresistive cantilevers. Next, trilayer cantilevers with shielded conductive tips are introduced for electrical AFM modes. Finally, ongoing research projects are touched upon, including approaches to fabricate hybrid-MEMS with single crystal silicon piezoresistors for improved sensitivity, and an analysis of reproducibility of fabricated trilayer cantilevers.

EPFL2022

A new versatile hybrid MEMS technology for high sensitivity, fluid proof sensing applications.

Matthias Neuenschwander

EPFL2022

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

EPFL2012