Publications associées à Microprocesseur

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Electronic readout of DNA amplification in nanoliter chambers. Strategies towards highly parallel semiconductor-based nucleic acid amplification testing

Saurabh Tomar

Polymerase chain reaction (PCR) has been the most significant driver in the field of nucleic acid testing (NAT) since its invention. Popularized as an abbreviation by the Covid-19 pandemic, PCR-based methods are the gold standard in the field of diagnostic ...

EPFL2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

500 MHz high resolution proximity sensors with fully integrated digital counter

Giovanni Boero, Nergiz Sahin Solmaz, Reza Farsi

We report on the design and characterization of two inductive proximity sensors based on LC oscillators operating at 500 MHz. The distance from the target is obtained by measuring the oscillation frequency variation. Both sensors contain an off-chip LC res ...

ELSEVIER SCI LTD2023

Comparison of Two in Pixel Source Follower Schemes for Deep Subelectron Noise CMOS Image Sensors

Christian Enz, Assim Boukhayma, Antonino Caizzone, Andrea Kraxner, Minhao Yang, Daniel Mathias Bold

This paper compares two in-pixel source follower stage designs for low noise CMOS image sensors embedded both on a same 5 mm by 5 mm chip fabricated in a 180 nm CIS process. The presented chip embeds two pixel variants, one based on a body-effect-canceled ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

David Atienza Alonso, Marina Zapater Sancho, Luis Maria Costero Valero, Darong Huang, Ali Pahlevan

Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of th ...

2022

Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse

This paper presents the set of simulation means used to develop the concept of N2C2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation ...

2021

3D-ICE 3.0: efficient nonlinear MPSoC thermal simulation with pluggable heat sink models

David Atienza Alonso, Marina Zapater Sancho, Federico Terraneo

The increasing power density in modern high-performance multi-processor system-on-chip (MPSoC) is fueling a revolution in thermal management. On the one hand, thermal phenomena are becoming a critical concern, making accurate and efficient simulation a nec ...

2021

Magnonic crystals with reconfigurable magnetic defects for spin-based microwave electronics

Korbinian Baumgärtl

Collective spin excitations can propagate in magnetically ordered materials in the form of waves. These so-called spin waves (SWs) or magnons are promising for low-power beyond-CMOS information processing, which does not rely anymore on the lossy movement ...

EPFL2021

Enhanced-performance integrated Resonant Switched-Capacitor and Buck DC-DC converters for application in extreme radiation and magnetic field environments

Giacomo Ripamonti

DC-DC converters based on Application Specific Integrated Circuits (ASICs) have been developed in this doctoral work for the High-Luminosity Large Hadron Collider (HL-LHC) experiments at CERN. They step down the voltage from a 2.5 V line and supply a load ...

EPFL2020