Carte mère

Résumé

La carte mère est le circuit imprimé qui supporte la plupart des composants et des connecteurs nécessaires au fonctionnement d'un compatible PC. Elle est essentiellement composée de circuits imprimés et de ports de connexion qui assurent la liaison de tous les composants et périphériques propres à un micro-ordinateur (disques durs (HDD/SSD), mémoire vive (RAM Random acces memory), microprocesseur, cartes filles) afin qu'ils puissent être reconnus et configurés par le microprocesseur grâce au programme contenu dans le BIOS (basic input output system) devant effectuer la configuration et le démarrage correct de tous les équipements. Introduction vignette|upright|Une carte mère de station de travail professionnelle Dell Precision T3600. C'est la carte principale d'un micro-ordinateur qui regroupe les circuits principaux pour l'alimentation et les données (bus) sous contrôle du chipset et du BIOS tels que :

les ports internes sous forme de pin (microprocesseur, ou courant

Source officielle

https://fr.wikipedia.org/wiki/Carte_m%C3%A8re

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The main objective of the course is to introduce the concept of space system design and engineering. The course will describe the various subsystems involved in the design of a satellite. It will also describe the techniques of systems engineering that are used to obtain a coherent satellite design.

This course consists of two parts:

architecture of automation systems, hands-on lab
handling of faults and failures in real-time systems, including fault-tolerant computing

Ce cours traite des divers domaines techniques intervenant dans la conception et la réalisation d'un bâtiment, soit : physique du bâtiment, structures, matériaux, construction et installations techniques; ceci dans une approche globale et transversale.

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Virtualized Execution Runtime for FPGA Accelerators in the Cloud

Mikhail Asiatici, Nithin George, Paolo Ienne

FPGAs offer high performance coupled with energy efficiency making them extremely attractive computational resources within a cloud ecosystem. However, to achieve this integration and make them easy to program, we first need to enable users with varying expertise to easily develop cloud applications that leverage FPGAs. With the growing size of FPGAs, allocating them monolithically to users can be wasteful due to potentially low device utilization. Hence, we also need to be able to dynamically share FPGAs among multiple users. To address these concerns, we propose a methodology and a runtime system that together simplify the FPGA application development process by providing: 1) a clean abstraction with high-level APIs for easy application development; 2) a simple execution model that supports both hardware and software execution; and 3) a shared memory-model which is convenient to use for the programmers. Akin to an operating system on a computer, our lightweight runtime system enables the simultaneous execution of multiple applications by virtualizing computational resources, i.e., FPGA resources and on-board memory, and offers protection facilities to isolate applications from each other. In this paper, we illustrate how these features can be developed in a lightweight manner and quantitatively evaluate the performance overhead they introduce on a small set of applications running on our proof of concept prototype. Our results demonstrate that these features only introduce marginal performance overheads. More importantly, by sharing resources for simultaneous execution of multiple user applications, our platform improves FPGA utilization and delivers higher aggregate throughput compared to accessing the device in a time-shared manner.

2017

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LinoSPAD: a time-resolved 256x1 CMOS SPAD line sensor system featuring 64 FPGA-based TDC channels running at up to 8.5 giga-events per second

Claudio Bruschini, Samuel Burri, Edoardo Charbon, Harald Arjan Robert Homulle

LinoSPAD is a reconfigurable camera sensor with a 256x 1 CMOS SPAD (single-photon avalanche diode) pixel array connected to a low cost Xilinx Spartan 6 FPGA. The LinoSPAD sensor's line of pixels has a pitch of 24 pm and 40% fill factor. The FPGA implements an array of 64 TDCs and histogram engines capable of processing up to 8.5 giga-photons per second. The LinoSPAD sensor measures 1.68 mmx6.8 mm and each pixel has a direct digital output to connect to the FPGA. The chip is bonded on a carrier PCB to connect to the FPGA motherboard. 64 carry chain based TDCs sampled at 400 MHz can generate a timestamp every 7.5 ns with a mean time resolution below 25 ps per code. The 64 histogram engines provide time-of n-arrival histograms covering up to 50 ns. An alternative mode allows the readout of 28 bit timestamps which have a range of up to 4.5 ms. Since the FPGA TDCs have considerable non-linearity we implemented a correction module capable of increasing histogram linearity at real-time. The TDC array is interfaced to a computer using a super-speed USB3 link to transfer over 150k histograms per second for the 12.5 ns reference period used in our characterization. After characterization and subsequent programming of the post-processing we measure an instrument response histogram shorter than 100 ps FWHM using a strong laser pulse with 50 ps FWHM. A timing resolution that when combined with the high fill factor makes the sensor well suited for a wide variety of applications from fluorescence lifetime microscopy over Raman spectroscopy to 3D timen-of-flight.

Spie-Int Soc Optical Engineering2016

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Piezoresistive n-Type 4H-SiC Pressure Sensor with Membrane Formed by Mechanical Milling

Terunobu Akiyama, Danick Briand, Nico de Rooij

A 4H-SiC pressure sensor with piezoresistive transducers, for harsh environment applications, e.g., high temperature (~650°C) and/or in corrosive chemicals is presented. The sensing membrane, 1 mm in diameter and 50 µm in thickness, was formed by milling (drilling) a bulk single crystal SiC wafer. Both transverse and longitudinal piezoresistors were formed on the membrane out of an n-type SiC epitaxial layer. Ohmic contacts were obtained with Ta/Ni/Pt metallization followed by annealing at 1000°C for 20 min. The sensor was assembled on a small board and characterized under hydrostatic pressures up to 60 bar at room temperature. The obtained pressure sensitivity was 268 µV/V/bar. The sensor chip was exposed in air at 600°C for 165 hours and changes in bridge resistance were measured.

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

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