Concept

Boîtier de circuit intégré

Publications associées (87)

Optimized Module Packaging for Silicon Heterojunction Solar Cells and Increased PID Resistance

Recent studies showed that silicon heterojunction (SHJ) solar cells can be prone to potential induced degradation (PID) when encapsulated with a low volume resistivity ethylene vinyl acetate (EVA). We perform PID test in humid conditions (85°C/85% RH) on g ...

EU PVSEC Proceedings2020

Cuprous Oxide Photoelectrodes for Photoelectrochemical Water Splitting towards Unassisted Solar Hydrogen Production

Linfeng Pan

To handle global problems of energy and environmental pollution, efforts have been made to harvest energy from sunlight. Photoelectrochemcal water splitting is an efficient way to achieve sustainable solar-fuel production. However, to make this method comp ...

EPFL2019

Efficient Workload Colocation in Modern Data Centers

Calin Iorgulescu

Despite the high costs of acquisition and maintenance of modern data centers, machine resource utilization is often low. Servers running online interactive services are over-provisioned to support peak load (which only occurs for a fraction of the time), d ...

EPFL2019

Rapid identification and interpretation of gene‐environment associations using the new R.SamBada landscape genomics pipeline

Stéphane Joost, Oliver Michele Selmoni, Estelle Rochat, Sylvie Stucki, Kevin Leempoel, Elia Vajana

Samβada is a genome‐environment association (GEA) software, designed to search for signatures of local adaptation. However, pre‐ and post‐processing of data can be labour‐intensive, preventing wider uptake of the method. We have now developed R.SamBada, an ...

2019

Computing with Ferroelectric FETs: Devices, Models, Systems, and Applications

Anisoara Ionescu

In this paper, we consider devices, circuits, and systems comprised of transistors with integrated ferroelectrics. Said structures are actively being considered by various semiconductor manufacturers as they can address a large and unique design space. Tra ...

IEEE2018

Semiconductor device comprising a three-dimensional field plate

Elison de Nazareth Matioli, Jun Ma

The present invention relates to a Semiconductor device including a first electrode, a second electrode and at least one semiconductor material or layer between the first and second electrode. The semiconductor device further includes at least one field pl ...

2018

Experimental setup and o-ring based μfluidic interface for suspended microchannel resonators

Annalisa De Pastina, Damien Maillard

Existing solutions for suspended microchannel resonators packaging - Fluidic delivery (back-side) : PDMS or o-ring sealing - Vacuum encapsulation (front-side) : glass capping or o-ring sealing Our suspended microchannel resonators have inlets and outlets o ...

2017

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Mohammad Amin Shokrollahi, Seyed Armin Tajalli, Christoph Walter, Ali Hormati, Anant Pratap Singh, Omid Talebi Amiri, Klaas Lammert Hofstra, Sergio Pesenti

High-speed signaling over package substrates is key to delivering the promise of 2.5D integration. Applications abound and include high-density memory interfaces, sub-division of large dies to increase yield and lower development time, sub-division of a di ...

2016

Solid-liquid interdiffusion (SLID) bonding in the Au-In system: experimental study and 1D modelling

Michel Rappaz, Aïcha Hessler-Wyser, Léa Deillon, Thierry Hessler

Au-In bonds with a nominal composition of about 60 at.% In were fabricated for use in wafer-level packaging of MEMS. The microstructure of the bonds was studied by scanning electron microscopy. The bond hermeticity was then assessed using oxidation of Cu t ...

Institute of Physics2015

Post-cmos processing and 3d integration based on dry-film lithography

Carlotta Guiducci, Yusuf Leblebici, Yüksel Temiz

A method for performing a post processing pattern on a diced chip having a foot-print, comprises the steps of providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the di ...

2015

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