Publications associées à Intel Pentium

Jitter Analysis and Measurement in Subthreshold Source-Coupled Differential Ring Oscillators

Seyed Armin Tajalli, Mahsa Shoaran, Yusuf Leblebici

The jitter and the phase noise of ring oscillators utilizing subthreshold source-coupled logic (STSCL) style are analyzed in this paper. Closed-form equations are derived to predict the jitter and phase noise caused by white and flicker noise. Measurement ...

2015

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Sotiria Fytraki, Evangelos Vlachos

Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools. As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring. A recu ...

2014

First principles study of As 2p core-level shifts at GaAs/Al2O3 interfaces

Alfredo Pasquarello, Giacomo Francesco Leonardo Miceli

Arsenic 2p core-level shifts at GaAs/Al2O3 interfaces are determined with respect to bulk GaAs through density functional calculations. Atomistic interface models are constructed in which As atoms are found in various chemical environments. Both Ga-termina ...

American Institute of Physics2013

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Giovanni De Micheli, Andreas Peter Burg, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Pascal Andreas Meinerzhagen

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

24 GHz LNA and Vector Modulator Phase Shifter for Phased-Array Receiver in CMOS Technology

Pierre-André Farine, Cyril Botteron, Gabriele Tasselli, Ban Wang

With the rapid development of the applications in short range communication, phased-array receiver working at 24 GHz can provide enhanced gain performance at desired transmission direction. Also there is the wide signal bandwidth, i.e. 250 MHz free license ...

2013

Task Scheduling for Highly Concurrent Analytical and Transactional Main-Memory Workloads

Anastasia Ailamaki, Iraklis Psaroudakis

Task scheduling typically employs a worker thread per hardware context to process a dynamically changing set of tasks. It is an appealing solution to exploit modern multi-core processors, as it eases parallelization and avoids unnecessary context switches ...

2013

Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Muhammad Umer Khalid

Multilevel gain-cell DRAMs are interesting to improve the area-efficiency of modern fault-tolerant systems-on-chip implemented in deep-submicron CMOS technologies. This paper addresses the problem of long access times in such multilevel gain-cell DRAMs, wh ...

Ieee2012

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

Edoardo Charbon, Ties Jan Henderikus Kluter, Claudio Favi, Christian Mester

We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor. In order to save power, data to and from Custom Instruction Units (CIUs) is synchronized via an optical s ...

2012

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Intel Pentium

Jitter Analysis and Measurement in Subthreshold Source-Coupled Differential Ring Oscillators

Monolithic 50x50 MEMS Silicon Photonic Switches with Microsecond Response Time

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Consistency Models in Distributed Systems with Physical Clocks

First principles study of As 2p core-level shifts at GaAs/Al2O3 interfaces

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

24 GHz LNA and Vector Modulator Phase Shifter for Phased-Array Receiver in CMOS Technology

Task Scheduling for Highly Concurrent Analytical and Transactional Main-Memory Workloads

Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

Graph Chatbot

Chattez avec Graph Search

Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM

Consistency Models in Distributed Systems with Physical Clocks

First principles study of As 2p core-level shifts at GaAs/Al2O3 interfaces

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Jitter Analysis and Measurement in Subthreshold Source-Coupled Differential Ring Oscillators

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

Monolithic 50x50 MEMS Silicon Photonic Switches with Microsecond Response Time

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Task Scheduling for Highly Concurrent Analytical and Transactional Main-Memory Workloads

24 GHz LNA and Vector Modulator Phase Shifter for Phased-Array Receiver in CMOS Technology