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A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation

Mahsa Shoaran, Uisub Shin, Cong Ding, Laxmeesha Somappa

Measuring neural oscillatory synchrony facilitates our understanding of complex brain networks and the underlying pathological states. Altering the cross-regional synchrony-as a measure of brain network connectivity-via phase-locked deep brain stimulation ...

IEEE2022

Oblivious Dynamic Searchable Encryption on Distributed Cloud Systems

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Dynamic Searchable Symmetric Encryption (DSSE) allows search/update operations over encrypted data via an encrypted index. However, DSSE has been shown to be vulnerable to statistical inference attacks, which can extract a significant amount of information ...

SPRINGER INTERNATIONAL PUBLISHING AG2018

Approximate 32-Bit Floating-Point Unit Design with 53% Power-Area Product Reduction

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

The floating-point unit is one of the most common building block in any computing system and is used for a huge number of applications. By combining two state-of-the-art techniques of imprecise hardware, namely Gate-Level Pruning and Inexact Speculative Ad ...

Ieee2016

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

HW-SW Implementation of a Decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs

Giovanni De Micheli, Jaime Joven Murillo

Nowadays industrial monoprocessor and multipro- cessor systems make use of hardware floating-point units (FPUs) to provide software acceleration and better precision due to the necessity to compute complex software applications. This paper presents the des ...

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Smart camera based on embedded HW/SW coprocessor

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This paper describes an image acquisition and a processing system based on a new coprocessor architecture designed for CMOS sensor imaging. The system exploits the full potential CMOS selective access imaging technology because the coprocessor unit is inte ...

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Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo

Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed varia ...

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