Architecture matérielle | EPFL Graph Search

vignette|Architecture matérielle d'un processeur Intel Core2. vignette|Architecture matérielle d'un Cyclops64 (BlueGene/C). L’architecture matérielle décrit l’agencement interne de composants électroniques ainsi que leurs interactions. Le terme interne employé ici permet de bien faire la différence avec l’architecture (externe) de processeur (ou architecture de jeu d'instruction), qui s'intéresse à la spécification fonctionnelle d'un processeur, du point de vue du programmeur en langage machine. Plusieurs architectures internes peuvent implémenter une même architecture externe. Microprocesseur Par défaut de langage, en parlant d’architecture matérielle (hardware) on pense immédiatement à architecture hardware autour d’un processeur. Un microprocesseur a accès à un ou plusieurs bus (AGP, PCI) afin de dialoguer avec les composants et les périphériques. L’architecture est souvent grandement masquée aux utilisateurs par le biais du système d'exploitation, qui donne une abstra

Détermination d’un protocole pour la construction d’un modèle en éléments finis d’un fémur à partir des images CT

Javier Manias, Alexandre Terrier

Dans ce projet, nous cherchons à définir un protocole ainsi que les points à améliorer pour créer un modèle d’éléments finis à partir des images CT d’un fémur cadavérique. La première étape, qui inclut la segmentation et le lissage de la géométrie, sert à générer la géométrie. La deuxième consiste en la réalisation du modèle CAD (computer aided design) en 3D. Une fois le modèle CAD crée, on génère automatiquement un maillage. Les forces musculaires simplifiées, représentant un cas de marche, sont appliquées. Pour finir, les propriétés mécaniques du modèle sont insérées à chaque noeud.

2008

Uncooperative Rendezvous in Space: Design of an Electronic Architecture for High Performance Avionic with Multi Sensor Input and Intensive Data Rate.

Michaël Yannick Juillard

Active Debris Removal missions consist of sending a satellite in space and removing one or more debris from their current orbit. A key challenge is to obtain information about the uncooperative target. By gathering the velocity, position, and rotation of the desired object, the satellite is able to plan its trajectory and define the sequence of approach. It requires the use of a variety of sensors with often a high data rate. For this task, a dedicated payload computer is envisioned with the responsibility of processing the information from the various rendezvous sensors. This component has the goal to provide meaningful information to the main satellite computer about the targeted debris. The focus of this work is on the data processing, the number of elements, and the electrical energy with constraints due to internal communication.First, an avionic testbench was built at the EPFL Space Center to assess early hardware and software architectures. The goal is to enable Hardware-In-the-Loop testing while developing the payload computer. A communication data bus has been implemented between the Platform and the Payload On-Board Computer. Emphasis was placed on the reliability of the high-level protocol and multiple concepts for improvement were analyzed.In a second phase, the testbench has been extended to support other data buses. The aim was to develop a reliable and efficient backup or fall-back data bus in case of failure in the main link. Four data buses have been tested with extensive analyses on their resilience to error and the efficiency of their data exchange.In parallel, extensive work has been performed to develop a simulation and optimization tool. Its goal is to support the design of payload avionic architectures for ADR missions by providing trade-offs and analyses. In the first iteration, a simulator has been created with instances of various high-level elements modeled.The second iteration introduced the additional dimension of optimization. It is trying to determine the best set of instruments and algorithms to use. With this capability, numerous analyses have been conducted on the influence of various parameters linked to the general optimizer behavior. It allows us to better understand the strength and limitations of the tool.The third step regarding the tool was to start its verification. The task has been to develop an Hardware-In-the-Loop architecture to compare its behavior with the results of the optimizer. The implementation of various mock-up algorithms enables the verification of their models in the tool. These analyses guarantee the feasibility of the outputted solution.The last part was dedicated to the creation and analysis of a realistic payload avionic architecture. The goal was to test the capability of the tool with hardware elements inspired by actual components. This work has shown the procedure to efficiently use the tool in the design phase of a mission.In conclusion, the work on the communication between the Payload and the Platform On-Board Computer has brought valuable lessons and experiences to the projects. They can now be used for the establishment of the high-level protocol into ClearSpace-1 flight software. In addition, the optimizer created allows tackling the design of complex payload avionic architecture where mass saving and processing resources are crucial. It is an essential point to develop a highly efficient payload computer for an Active Debris Removal satellite.

EPFL2022

Scalable Simulation Methodologies for Many-Core Heterogeneous Systems

Shivani Raghav

With increasing complexity and performance demands of emerging compute-intensive data-parallel workloads, many-core computing systems are becoming a popular trend in computer design. Fast and scalable simulation methods are needed to make meaningful predictions of design alternatives to prepare early software development and to assess the performance of a system before the real hardware is available. However, simulation technology for large-scale, many-core systems is lagging behind. Most of the existing simulation techniques are slow and complex or have poor scalability and high cost of development, which leads to an unacceptable performance when simulating a large number of cores. New challenges brought by emerging many-core systems demand new methods for simulating these platforms. This thesis investigates the techniques for improving the performance of parallel simulators to model many-core heterogeneous architectures. With the recent advances in programmability and processing power of graphical hardware, General Purpose Graphical Processing Units (GPGPUs) are becoming a popular host platform for solving broad range of computationally expensive problems. The easy availability of low cost, highly parallel GPGPU platforms presents an opportunity for accelerating architectural simulations. In this thesis, I propose and investigate a novel idea of using GPGPUs as a host platform for accelerating simulation of many-core systems. GPGPUs are most suitable for certain specific highly parallel workloads with fine-grained multi-threading and high computational intensity. Architectural simulation, on the other hand, is an extremely complex task with numerous dependencies and rules. To this end, I first determine the feasibility of accelerating various target many-core architectures at different levels of abstraction details, considering the particularities of prevalent GPU architectures and their programming models. Based on this study, I target a heterogeneous architecture of a multi-core CPU connected to many-core coprocessors for GPGPU acceleration. I propose ways to exploit ample parallelism in many-core simulation and present a comprehensive framework to develop an architecture-independent, fast, scalable, easy-to-use, full-system simulator. In particular, I outline some of the challenges faced and insights gained using our proposed approach. I present specific methods and approaches that maximize the throughput of GPU power and memory bandwidth allowing optimized parallelization with minimal synchronization. Our results show high scalability and high speed up in performance for simulating up to eight thousand cores.

EPFL2014