Concept

Zero ASIC

Zero ASIC Corporation, formerly Adapteva, Inc., is a fabless semiconductor company focusing on low power many core microprocessor design. The company was the second company to announce a design with 1,000 specialized processing cores on a single integrated circuit. Adapteva was founded in 2008 with the goal of bringing a ten times advancement in floating-point performance per watt for the mobile device market. Products are based on its Epiphany multi-core multiple instruction, multiple data (MIMD) architecture and its Parallella Kickstarter project promoting "a supercomputer for everyone" in September 2012. The company name is a combination of "adapt" and the Hebrew word "Teva" meaning nature. Adapteva was founded in March 2008, by Andreas Olofsson. The company was founded with the goal of bringing a 10× advancement in floating-point processing energy efficiency for the mobile device market. In May 2009, Olofsson had a prototype of a new type of massively parallel multi-core computer architecture. The initial prototype was implemented in 65 nm and had 16 independent microprocessor cores. The initial prototypes enabled Adapteva to secure US$1.5 million in series-A funding from BittWare, a company from Concord, New Hampshire, in October 2009. Adapteva's first commercial chip product started sampling to customers in early May 2011 and they soon thereafter announced the capability to put up to 4,096 cores on a single chip. The Epiphany III, was announced in October 2011 using 28 nm and 65 nm manufacturing processes. Adapteva's main product family is the Epiphany scalable multi-core MIMD architecture. The Epiphany architecture could accommodate chips with up to 4,096 RISC out-of-order microprocessors, all sharing a single 32-bit flat memory space. Each RISC processor in the Epiphany architecture is superscalar with 64× 32-bit unified register file (integer or single-precision) microprocessor operating up to 1 GHz and capable of 2 GFLOPS (single-precision).

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Cours associés (2)
CS-307: Introduction to multiprocessor architecture
Multiprocessors are a core component in all types of computing infrastructure, from phones to datacenters. This course will build on the prerequisites of processor design and concurrency to introduce
CS-471: Advanced multiprocessor architecture
Multiprocessors are now the defacto building blocks for all computer systems. This course will build upon the basic concepts offered in Computer Architecture I to cover the architecture and organizati
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Tableaux de portes programmables sur le terrain (FPGA)
Couvre les principes de base et l'architecture des FPGA (Field Programmable Gate Arrays) et leurs options de mise en œuvre pour les circuits numériques.
Dispositifs logiques programmables : introduction à GAL et CPLD
Présente GAL et CPLD, couvrant l'évolution PAL, les limitations GAL et l'architecture CPLD.
Spécialisation Hardware
Explore la spécialisation matérielle, les avantages ASIC par rapport aux processeurs et les stratégies pour atteindre des efficacités de type ASIC dans la conception des puces.
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Publications associées (33)

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HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

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Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...
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Concepts associés (9)
Manycore processor
Manycore processors are special kinds of multi-core processors designed for a high degree of parallel processing, containing numerous simpler, independent processor cores (from a few tens of cores to thousands or more). Manycore processors are used extensively in embedded computers and high-performance computing. Manycore processors are distinct from multi-core processors in being optimized from the outset for a higher degree of explicit parallelism, and for higher throughput (or lower power consumption) at the expense of latency and lower single-thread performance.
Vision processing unit
A vision processing unit (VPU) is (as of 2023) an emerging class of microprocessor; it is a specific type of AI accelerator, designed to accelerate machine vision tasks. Vision processing units are distinct from video processing units (which are specialised for video encoding and decoding) in their suitability for running machine vision algorithms such as CNN (convolutional neural networks), SIFT (scale-invariant feature transform) and similar.
Scratchpad memory
Scratchpad memory (SPM), also known as scratchpad, scratchpad RAM or local store in computer terminology, is an internal memory, usually high-speed, used for temporary storage of calculations, data, and other work in progress. In reference to a microprocessor (or CPU), scratchpad refers to a special high-speed memory used to hold small items of data for rapid retrieval. It is similar to the usage and size of a scratchpad in life: a pad of paper for preliminary notes or sketches or writings, etc.
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