Manycore processor | EPFL Graph Search

Manycore processors are special kinds of multi-core processors designed for a high degree of parallel processing, containing numerous simpler, independent processor cores (from a few tens of cores to thousands or more). Manycore processors are used extensively in embedded computers and high-performance computing. Contrast with multicore architecture Manycore processors are distinct from multi-core processors in being optimized from the outset for a higher degree of explicit parallelism, and for higher throughput (or lower power consumption) at the expense of latency and lower single-thread performance. The broader category of multi-core processors, by contrast, are usually designed to efficiently run both parallel and serial code, and therefore place more emphasis on high single-thread performance (e.g. devoting more silicon to out of order execution, deeper pipelines, more superscalar execution units, and larger, more general caches), and shared memory. These techniques

Efficient Communication and Synchronization on Manycore Processors

Darko Petrovic

The increased number of cores integrated on a chip has brought about a number of challenges. Concerns about the scalability of cache coherence protocols have urged both researchers and practitioners to explore alternative programming models, where cache coherence is not a given. Message passing, traditionally used in distributed systems, has surfaced as an appealing alternative to shared memory, commonly used in multiprocessor systems. In this thesis, we study how basic communication and synchronization primitives on manycore processors can be improved, with an accent on taking advantage of message passing. We do this in two different contexts: (i) message passing is the only means of communication and (ii) it coexists with traditional cache-coherent shared memory. In the first part of the thesis, we analytically and experimentally study collective communication on a message-passing manycore processor. First, we devise broadcast algorithms for the Intel SCC, an experimental manycore platform without coherent caches. Our ideas are captured by OC-Bcast (on-chip broadcast), a tree-based broadcast algorithm. Two versions of OC-Bcast are presented: One for synchronous communication, suitable for use in high-performance libraries implementing the Message Passing Interface (MPI), and another for asynchronous communication, for use in distributed algorithms and general-purpose software. Both OC-Bcast flavors are based on one-sided communication and significantly outperform (by up to 3x) state-of-the-art two-sided algorithms. Next, we conceive an analytical communication model for the SCC. By expressing the latency and throughput of different broadcast algorithms through this model, we reveal that the advantage of OC-Bcast comes from greatly reducing the number of off-chip memory accesses on the critical path. The second part of the thesis focuses on lock-based synchronization. We start by introducing the concept of hybrid mutual exclusion algorithms, which rely both on cache-coherent shared memory and message passing. The hybrid algorithms we present, HybLock and HybComb, are shown to significantly outperform (by even 4x) their shared-memory-only counterparts, when used to implement concurrent counters, stacks and queues on a hybrid Tilera TILE-Gx processor. The advantage of our hybrid algorithms comes from the fact that their most critical parts rely on message passing, thereby avoiding the overhead of the cache coherence protocol. Still, we take advantage of shared memory, as shared state makes the implementation of certain mechanisms much more straightforward. Next, we try to profit from these insights even on processors without hardware support for message passing. Taking two classic x86 processors from Intel and AMD, we come up with cache-aware optimizations that improve the performance of executing contended critical sections by as much as 6x.

EPFL2015

DSPE: Domain Specific Language for Parallel Real-Time Stream Processing

Tiziano Leidi

Today, the evolution of software solutions for parallel processing is strong, as a consequence of the mainstream introduction of chip-level multiprocessors. These types of parallel processors, which include general-purpose multi-cores and graphical processing units (GPUs), allow the execution of very intensive computations. However, depending on the nature of the executed applications, their effective exploitation may represent a complex task. In terms of parallel processing, the family of stream-processing applications is appealing because it features some forms of parallelism that may be exploited systematically. However, the processing performed by these types of applications is often real-time and, therefore, special-purpose support for parallel processing is required. The main contribution of this thesis is the DIGITAL STREAM-PROCESSING ENVIRONMENT (DSPE): an open-source development environment for rapid prototyping and customizing parallel real-time stream-processing applications. DSPE features a domain-specific language (DSL) based on model-driven generative programming that allows specifying applications at a high abstraction level. From the information provided with the DSL, generators are utilized to automatically produce the source code of applications. The source code generated by DSPE features dedicated infrastructures for parallel processing in stream-processing applications. These infrastructures are based on event-driven scheduling and on dynamic load balancing of lightweight tasks, which are techniques that limit the impact of load imbalances when parallel stream processing. Furthermore, DSPE supports the integration of kernels for GPUs for the exploitation of heterogeneous combinations of multi-core processors and GPUs. In DSPE, the generated source code can be configured to fit application- and hardware-specific needs. Furthermore, profile-guided, model-to-model transformations ease the migration from a serial version of an application to a parallel processing version. Experiments performed with DSPE on micro-benchmarks and sample applications demonstrate that the adopted approaches facilitate obtaining linear or near-to-linear scalings of the speed-up, when progressively incrementing the number of utilized processor cores.

EPFL2012