Publications associées à Bit

EdgeAI-Aware Design of In-Memory Computing Architectures

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, Flavio Ponzina

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

2023

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, Flavio Ponzina

The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

2022

Full key recovery side-channel attack against ephemeral SIKE on the Cortex-M4

Aymeric Genet, Natacha Yolande Emmanuel Marie Linard de Guertechin, Novak Kaluderovic

This paper describes the first practical single-trace side-channel power analysis of SIKE. While SIKE is a post-quantum key exchange, the scheme still relies on a secret elliptic curve scalar multiplication which involves a loop of a double-and-add procedu ...

2021

Six shades lighter: a bit-serial implementation of the AES family

Subhadeep Banik, Muhammed Fatih Balli, Sergio Roldán Lombardía

Recently, cryptographic literature has seen new block cipher designs such as PRESENT, GIFT or SKINNY that aim to be more lightweight than the current standard, i.e., AES. Even though AES family of block ciphers were designed two decades ago, they still rem ...

2021

Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Wr ...

IEEE2020

The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits

Subhadeep Banik, Muhammed Fatih Balli, Andrea Felice Caforio

The bit-sliding paper of Jean et al. (CHES 2017) showed that the smallest-size circuit for SPN based block ciphers such as AES, SKINNY and PRESENT can be achieved via bit-serial implementations. Their technique decreases the bit size of the datapath and na ...

2020

Reconfigurable logic circuit

Edoardo Charbon, Francesco Regazzoni

The present invention relates to a reconfigurable logic circuit comprising - a first, second and third switching circuit arranged for receiving a first input bit, a second input bit and a third input bit, respectively, and each arranged for being configure ...

2020

Systems and methods for rate-compatible polar codes for general channels

Seyed Hamed Hassani, Marco Mondelli

According to certain embodiments, a transmit node in a wireless communications system includes a first universal rate-compatible polar encoder and a transmitter. The first universal rate-compatible polar encoder is configured for a family of two or more ty ...

2019

Bits through Time

Elie Najm

In any communication system, there exist two dimensions through which the information at the source becomes distorted before reaching the destination: the noisy channel and time. Messages transmitted through a noisy channel are susceptible to modification ...

EPFL2019