Publications related to Bit | EPFL Graph Search

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, Flavio Ponzina

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

2023

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, Flavio Ponzina

The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

2022

Horizontal side-channel full key recovery on ephemeral SIKE

Natacha Yolande Emmanuel Marie Linard de Guertechin, Aymeric Genet, Novak Kaluderovic

This paper describes the first practical single-trace side-channel power analysis of SIKE. The attack exploits the nature of elliptic curve point addition formulas which require the same function to be executed multiple times. We target the three point lad ...

2021

Six shades lighter: a bit-serial implementation of the AES family

Subhadeep Banik, Muhammed Fatih Balli, Sergio Roldán Lombardía

Recently, cryptographic literature has seen new block cipher designs such as PRESENT, GIFT or SKINNY that aim to be more lightweight than the current standard, i.e., AES. Even though AES family of block ciphers were designed two decades ago, they still rem ...

2021

Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Wr ...

IEEE2020

The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits

Andrea Felice Caforio, Subhadeep Banik, Muhammed Fatih Balli

The bit-sliding paper of Jean et al. (CHES 2017) showed that the smallest-size circuit for SPN based block ciphers such as AES, SKINNY and PRESENT can be achieved via bit-serial implementations. Their technique decreases the bit size of the datapath and na ...

2020

Reconfigurable logic circuit

Edoardo Charbon, Francesco Regazzoni

The present invention relates to a reconfigurable logic circuit comprising - a first, second and third switching circuit arranged for receiving a first input bit, a second input bit and a third input bit, respectively, and each arranged for being configure ...

2020

Megapixel time-gated SPAD image sensor for 2D and 3D imaging applications

Edoardo Charbon, Claudio Bruschini, Ivan Michel Antolovic, Andrei Ardelean, Ming-Lo Wu, Arin Can Ülkü, Kazuhiro Morimoto

We present a 1 Mpixel single-photon avalanche diode camera featuring 3.8 ns time gating and 24 kips frame rate, fabricated in 180 nm CMOS image sensor technology. We designed two pixels with a pitch of 9.4 mu m in 7 T and 5.75 T configurations respectively ...

OPTICAL SOC AMER2020

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