Publications associées à X86

Resolve: Enabling Accurate Parallel Monitoring under Relaxed Memory Models

Babak Falsafi, Sotiria Fytraki, Evangelos Vlachos

Hardware-assisted instruction-grain monitoring frameworks provide high-coverage, low overhead debugging support for parallel programs. Unfortunately, existing frameworks are ill-suited for the relaxed memory models employed by nearly all modern processor a ...

2014

SIMinG-1k: A thousand-core simulator running on general-purpose graphical processing units

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

This paper introduces SIMinG-1k-a manycore simulator infrastructure. SIMinG-1k is a graphics processing unit accelerated, parallel simulator for design-space exploration of large-scale manycore systems. It features an optimal trade-off between modeling acc ...

Wiley-Blackwell2013

FireBird: PowerPC e200 Based SoC for High Temperature Operation

Andreas Peter Burg, Yusuf Leblebici, Thomas Maeder, Pascal Andreas Meinerzhagen, Conor Joseph Slater, Ömer Cogal, Carl Christian Sten Dominic Senning, Radisav Cojbasic

PowerPC Architecture microcontrollers are commonly used in embedded applications. In this work we present FireBird, the first PowerPC based SoC for reliable operation beyond 200C. It is a significant challenge to design SoCs for reliable operation at high ...

2013

Boosting Binary Keypoint Descriptors

Pascal Fua, Vincent Lepetit, Tomasz Piotr Trzcinski, Christos Marios Christoudias

Binary keypoint descriptors provide an efficient alternative to their floating-point competitors as they enable faster processing while requiring less memory. In this paper, we propose a novel framework to learn an extremely compact binary descriptor we ca ...

2013

Markov Decision Process Based Energy-Efficient On-Line Scheduling for Slice Parallel Video Decoders on Multicore Systems

Pascal Frossard, David Atienza Alonso, Karim Kanoun

We consider the problem of energy-efficient on-line scheduling for slice-parallel video decoders on multicore systems. We assume that each of the processors are Dynamic Voltage Frequency Scaling (DVFS) enabled such that they can independently trade off per ...

Ieee-Inst Electrical Electronics Engineers Inc2013

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

Bringing Virtualization to the x86 Architecture with the Original VMware Workstation

Edouard Bugnion

This article describes the historical context, technical challenges, and main implementation techniques used by VMware Workstation to bring virtualization to the x86 architecture in 1999. Although virtual machine monitors (VMMs) had been around for decades ...

Association for Computing Machinery2012

An Architecture-Independent Instruction Shuffler to Protect against Side-Channel Attacks

Paolo Ienne, Ali Galip Bayrak, Wayne Burleson, Nikola Velickovic

Embedded cryptographic systems, such as smart cards, require secure implementations that are robust to a variety of low-level attacks. Side-Channel Attacks (SCA) exploit the information such as power consumption, electromagnetic radiation and acoustic leak ...

2012

TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing

David Atienza Alonso, Andreas Peter Burg, Pascal Andreas Meinerzhagen, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan, Oskar Andersson

Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ul ...

2012

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X86

Resolve: Enabling Accurate Parallel Monitoring under Relaxed Memory Models

SIMinG-1k: A thousand-core simulator running on general-purpose graphical processing units

FireBird: PowerPC e200 Based SoC for High Temperature Operation

Boosting Binary Keypoint Descriptors

Near- and Sub-Threshold Design for Ultra-Low-Power Embedded Systems

Markov Decision Process Based Energy-Efficient On-Line Scheduling for Slice Parallel Video Decoders on Multicore Systems

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Bringing Virtualization to the x86 Architecture with the Original VMware Workstation

An Architecture-Independent Instruction Shuffler to Protect against Side-Channel Attacks

TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing

Graph Chatbot

Chattez avec Graph Search

Boosting Binary Keypoint Descriptors

Resolve: Enabling Accurate Parallel Monitoring under Relaxed Memory Models

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

An Architecture-Independent Instruction Shuffler to Protect against Side-Channel Attacks

TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing

SIMinG-1k: A thousand-core simulator running on general-purpose graphical processing units

FireBird: PowerPC e200 Based SoC for High Temperature Operation

Near- and Sub-Threshold Design for Ultra-Low-Power Embedded Systems

Markov Decision Process Based Energy-Efficient On-Line Scheduling for Slice Parallel Video Decoders on Multicore Systems

Bringing Virtualization to the x86 Architecture with the Original VMware Workstation