Concept

Transistor model

Publications associées (48)

Nonlinear Photoluminescence in Gold Thin Films

Promisingapplications in photonics are driven by the ability tofabricate crystal-quality metal thin films of controlled thicknessdown to a few nanometers. In particular, these materials exhibit ahighly nonlinear response to optical fields owing to the indu ...

AMER CHEMICAL SOC2023

Study of Donor-like Surface Trap Emission in GaN HEMTs

Farzan Jazaeri

Gate-lag induced trapping effects due to donor-like surface traps located in the access regions between the electrodes of AlGaN/GaN HEMTs are investigated through TCAD transient simulations. The effects of variation in trap energy level and temperature on ...

IEEE2021

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both with ...

ASSOC COMPUTING MACHINERY2020

Comparison of Different Precision Pseudo Resistor Realizations in the DC-Feedback of Capacitive Transimpedance Amplifiers

Georg Fantner, Jens Anders

In this paper, three different pseudo resistor (PR) realizations are compared regarding their noise and linearity performance within the DC feedback loop of an integrator-differentiator transimpedance amplifier (I-D-TIA). Thanks to its intrinsic shot noise ...

IEEE2019

Experimental g(m)/I-D Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Jean-Michel Sallese, Christophe Lallement

Transconductance efficiency (g(m)/I-D) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of g(m)/I-D versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully deple ...

2018

Conformal Deposition of Conductive Single-Crystalline Cobalt Silicide Layer on Si Wafer via a Molecular Approach

Giovanni De Micheli, Olha Sereda, Pierre-Emmanuel Julien Marc Gaillardon, Tsung-Han Lin, David Baudouin

The realization of metal-semiconductor contacts plays a significant role in ultrascaled integrated circuits. Here, we establish a low-temperature molecular approach for the conformal deposition of a 20-nm Co-rich layer on Si (100) wafers by reaction in sol ...

2018

Low Temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology through an Organometallic Approach

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Michele De Marchi, Maxime Victor Thammasack, Tsung-Han Lin, David Baudouin

The race for performance of integrated circuits is nowadays facing a downscale limitation. To overpass this nanoscale limit, modern transistors with complex geometries have flourished, allowing higher performance and energy efficiency. Accompanying this br ...

Amer Chemical Soc2017

Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs

Matthias Bucher, Mathieu Yves Hervé Coustans

Variability of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) is an important concern for many analog CMOS integrated circuits. In this paper, transistors with enclosed gate layout are examined and compared with standard layout transistors, wit ...

IEEE2017

Conformal Mapping of Impedance Stability Models for System-Level Dynamics Assessments

Drazen Dujic, Francisco Daniel Freijedo Fernández, Uzair Javaid

Impedance stability methods are suitable for assessing the dynamics of power converters controllers, but also for ac/dc microgrids system level studies. This work proposes the combination of impedance modeling and conformal mapping for the identification o ...

2017

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

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