Publications associées à Amplificateur de détection

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

David Atienza Alonso, Marina Zapater Sancho, Marco Antonio Rios, William Andrew Simon

A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a p ...

2021

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Miguel Peon Quiros, Marco Antonio Rios

Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a "simple'' repl ...

IEEE2020

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Robert Giterman, Odem Harel

Embedded memories, mostly implemented with static random access memory (SRAM), dominate the area and power of integrated circuits. Gain-cell embedded DRAM (GC-eDRAM) is an alternative to SRAM due to its high density, low power consumption, and two-ported f ...

ELSEVIER SCI LTD2020

Design Guidelines for High-Performance SCM Hierarchies

Babak Falsafi, Edouard Bugnion, Alexandros Daglis, Javier Picorel Obando, Mark Johnathon Sutherland, Dionysios Pnevmatikatos, Dmitrii Ustiugov

With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a fewfactors of DRAM. Nevertheless, the latency-sensitive nature of memory-residen ...

ACM2018

An Accelerator for High Efficient Vision Processing

Paolo Ienne, Robert Fasthuber, Zidong Du, Qi Guo

In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency a ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Paolo Ienne, Hossein Asadi, Sadegh Yazdanshenas

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM rela ...

Institute of Electrical and Electronics Engineers2016

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology

Davide Sacchetto, Yusuf Leblebici, Jury Sandrini, Tugba Demirci, Maxime Victor Thammasack

This paper presents a read-write design solution for passive ReRAM crossbar memory arrays to overcome the sneak current paths problem. The proposed circuitry includes an auto-calibration feature to overcome the sneak current effects during the READ operati ...

2015

ShiDianNao: shifting vision processing closer to the sensor

Paolo Ienne, Robert Fasthuber, Zidong Du

ACM2015

Scaling the Memory Power Wall with DRAM-Aware Data Management

Anastasia Ailamaki, Raja Appuswamy, Matthaios Alexandros Olma

Improving the energy efficiency of database systems has emerged as an important topic of research over the past few years. While significant attention has been paid to optimizing the power consumption of tradition disk-based databases, little attention has ...

ACM2015

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Amplificateur de détection

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Design Guidelines for High-Performance SCM Hierarchies

An Accelerator for High Efficient Vision Processing

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology

ShiDianNao: shifting vision processing closer to the sensor

Design of High-Temperature SRAM for Reliable Operation Beyond 250 C

Scaling the Memory Power Wall with DRAM-Aware Data Management

Graph Chatbot

Chattez avec Graph Search

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

An Accelerator for High Efficient Vision Processing

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology

Design Guidelines for High-Performance SCM Hierarchies

ShiDianNao: shifting vision processing closer to the sensor

Scaling the Memory Power Wall with DRAM-Aware Data Management

Design of High-Temperature SRAM for Reliable Operation Beyond 250 C