Publications associées à Unité de calcul en virgule flottante

A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication

David Atienza Alonso, Giovanni Ansaloni, Grégoire Axel Eggermann, Marco Antonio Rios

State-of-the-art Artificial Intelligence (AI) algorithms, such as graph neural networks and recommendation systems, require floating-point computation of very large matrix multiplications over sparse data. Their execution in resource-constrained scenarios, ...

2023

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi, Joshua Alexander Harrison Klein

Transformer models have achieved impressive results in various AI scenarios, ranging from vision to natural language processing. However, their computational complexity and their vast number of parameters hinder their implementations on resource-constraine ...

2023

Efficient Lung Nodule Detection via 3D Deep Learning with Shifted Convolutions

Jiancheng Yang, Bo Du, Kang Yuan

The high computational costs of deep convolutional neural networks hinder their deployment in real-world applications, including pulmonary nodule detection from CT scans where large 3D image sizes amplify the issue. This paper presents a novel 3D method to ...

IEEE2023

A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation

Mahsa Shoaran, Uisub Shin, Cong Ding, Laxmeesha Somappa

Measuring neural oscillatory synchrony facilitates our understanding of complex brain networks and the underlying pathological states. Altering the cross-regional synchrony-as a measure of brain network connectivity-via phase-locked deep brain stimulation ...

IEEE2022

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Irem Boybat Kara, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein, Abu Sebastian

Analog in-memory computing (AIMC) cores offers significant performance and energy benefits for neural network inference with respect to digital logic (e.g., CPUs). AIMCs accelerate matrix-vector multiplications, which dominate these applications’ run-time. ...

2022

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS2

Andras Kis, Guilherme Migliato Marega

Two-dimensional materials (2DMs) have found potential applications in many areas of electronics, such as sensing, memory systems, optoelectronics, and power. Despite an intense experimental work, the literature is lacking of accurate modeling of nonvolatil ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Touradj Ebrahimi

Joint Photographic Experts Group (JPEG) XS is a new International Standard from the JPEG Committee (formally known as ISO/International Electrotechnical Commission (IEC) JTC1/SC29/WG1). It defines an interoperable, visually lossless low-latency lightweight ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Biosensors for Bimolecular Computing: a Review and Future Perspectives

Sandro Carrara, Danilo Demarchi, Simone Aiassa

Biomolecular computing is the field of engineering where computation, storage, communication, and coding are obtained by exploiting interactions between biomolecules, especially DNA, RNA, and enzymes. They are a promising solution in a long-term vision, br ...

SPRINGER2020

ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning

Irem Boybat Kara, Evangelos Eleftheriou, Abu Sebastian

Deep neural networks (DNNs) have surpassed human-level accuracy in a variety of cognitive tasks but at the cost of significant memory/time requirements in DNN training. This limits their deployment in energy and memory limited applications that require rea ...

IEEE2020

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Unité de calcul en virgule flottante

Towards General-Purpose Decentralized Computing with Permissionless Extensibility

A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

Efficient Lung Nodule Detection via 3D Deep Learning with Shifted Convolutions

A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS2

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Biosensors for Bimolecular Computing: a Review and Future Perspectives

ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning

Graph Chatbot

Chattez avec Graph Search

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation

Efficient Lung Nodule Detection via 3D Deep Learning with Shifted Convolutions

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS2

ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Biosensors for Bimolecular Computing: a Review and Future Perspectives

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning