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Publications associées (381)

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Carlotta Guiducci, Yusuf Leblebici, Yüksel Temiz

This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Shashi Kanth Bobba, Michele De Marchi

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

2013

An LCD Tachistoscope With Sub-Millisecond Precision

Michael Herzog, Marc Repnow

Tachistoscopes allow brief visual stimulation delivery, crucial for experiments where subliminal presentation is required. Up to now, tachistoscopes have shortcomings regarding timing accuracy, reliability, and flexibility of use. Here, we present a new an ...

2013

Toward Scalable Transaction Processing -- Evolution of Shore-MT

Anastasia Ailamaki, Frederick Ryan Johnson, Pinar Tözün, Ippokratis Pandis

Designing scalable transaction processing systems on modern multicore hardware has been a challenge for almost a decade. The typical characteristics of transaction processing workloads lead to a high degree of unbounded communication on multicores for conv ...

VLDB Endowment2013

A Qos-Enabled On-Die Interconnect Fabric For Kilo-Node Chips

Boris Robert Grot

To meet rapidly growing performance demands and energy constraints, future chips will likely feature thousands of on-die resources. Existing network-on-chip solutions weren't designed for scalability and will be unable to meet future interconnect demands. ...

2012

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers

Giovanni De Micheli, Babak Falsafi, Boris Robert Grot, Ciprian Seiculescu, Stavros Volos, Naser Khosro Pour

Manycore chips are emerging as the architecture of choice to provide power efficiency and improve performance, while riding Moore’s Law. In these architectures, on-chip interconnects play a pivotal role in ensuring power and performance scalability. As sup ...

2012

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

Edoardo Charbon, Ties Jan Henderikus Kluter, Claudio Favi, Christian Mester

We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor. In order to save power, data to and from Custom Instruction Units (CIUs) is synchronized via an optical s ...

2012

Two Dimensional Array of Nanomechanical Membrane-type Surface Stress Sensor (MSS) with Improved Sensitivity

Nico de Rooij, Terunobu Akiyama, Sebastian Gautsch, Peter Vettiger, Frédéric Loizeau

We present a new generation of nanomechanical membrane-type surface stress sensor (MSS) chip, which has a two dimensional (2D) array of MSS on a single chip. The implementation of several techniques in design and microfabrication improves the sensitivity, ...

2012

Design Methods and Tools for Application-Specific Predictable Networks-on-Chip

Ciprian Seiculescu

As the complexity of applications grows with each new generation, so does the demand for computation power. To satisfy the computation demands at manageable power levels, we see a shift in the design paradigm from single processor systems to Multiprocessor ...

EPFL2012

A High-throughput and Low-Latency Interconnection Network for Multi-Core Clusters with 3-D Stacked L2 Tightly-Coupled Data Memory

Giovanni De Micheli, Luca Benini

The performance of most digital systems today is limited by the interconnect latency between logic and memory, rather than by the performance of logic or memory itself. Three- dimensional (3-D) integration using through-silicon-vias (TSVs) may provide a so ...

2012

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