Publications associées à Réseau sur une puce

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Yusuf Leblebici, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos

A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecti ...

2012

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Michail Zervas, Yusuf Leblebici, Alessandro Cevrero, Yüksel Temiz, Giulia Beanato, Panagiotis Athanasopoulos, Paolo Giovannini

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

2012

Two Dimensional Array of Piezoresistive Nanomechanical Membrane-Type Surface Stress Sensor(MSS) with Improved Sensitivity

Nico de Rooij, Terunobu Akiyama, Sebastian Gautsch, Peter Vettiger, Frédéric Loizeau

We present a new generation of piezoresistive nanomechanical Membrane-type Surface stress Sensor(MSS) chips, which consist of a two dimensional array of MSS on a single chip. The implementation of several optimization techniques in the design and microfabr ...

Mdpi Ag2012

Controlled Multi-Wavelength Emission in Full CMOS Compatible Micro-Lasers for on Chip Interconnections

We report on a system to control the emitted wavelength of a laser independently from its pump conditions. To illustrate the concept, it is applied to III-V microdisk lasers fabricated on a CMOS pilot line for application to multicolored optical interconne ...

Ieee-Inst Electrical Electronics Engineers Inc2012

A Fully Integrated 0.18-um CMOS Transceiver Chip for X-Band Phased-Array Systems

Kiarash Gharibdoust

An X-band core chip is designed and fabricated in 0.18-um CMOS technology, which can significantly reduce the monolithic microwave integrated circuit count required for realizing an active beam-former T/R module. The core chip consists of two RX/TX paths, ...

Institute of Electrical and Electronics Engineers2012

Full System Simulation of Many-Core Heterogeneous SoCs using GPU and QEMU Semihosting

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Modern system-on-chips are evolving towards complex and heterogeneous platforms with general-purpose processors coupled with massively parallel manycore accelerator fabrics (e.g. embedded GPUs). Platform developers are looking for efficient full-system sim ...

2012

Low-power clock distribution networks for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional cl ...

2012

Effects of Process Variations on 3-D Global Clock Distribution Networks

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this ...

Assoc Computing Machinery2012

When the ARM weakly consistent memory model meets speculation: is it necessary?

Tao-Chun Lee, Marc-Alexandre Boéchat

Aggressive memory-level-parallelism techniques have provided significant performance gain in Distributed Share Memory Designs. In this paper, we reevaluate speculative memory ordering in the context of Chip Multi-Processors (CMPs) and power-limited computa ...

2012

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Réseau sur une puce

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Two Dimensional Array of Piezoresistive Nanomechanical Membrane-Type Surface Stress Sensor(MSS) with Improved Sensitivity

Controlled Multi-Wavelength Emission in Full CMOS Compatible Micro-Lasers for on Chip Interconnections

A Fully Integrated 0.18-um CMOS Transceiver Chip for X-Band Phased-Array Systems

Full System Simulation of Many-Core Heterogeneous SoCs using GPU and QEMU Semihosting

Low-power clock distribution networks for 3-D ICs

Effects of Process Variations on 3-D Global Clock Distribution Networks

A 3D ALE Finite Element Method for Two-Phase Flows with Phase Change

When the ARM weakly consistent memory model meets speculation: is it necessary?

Graph Chatbot

Chattez avec Graph Search

A 3D ALE Finite Element Method for Two-Phase Flows with Phase Change

Controlled Multi-Wavelength Emission in Full CMOS Compatible Micro-Lasers for on Chip Interconnections

Two Dimensional Array of Piezoresistive Nanomechanical Membrane-Type Surface Stress Sensor(MSS) with Improved Sensitivity

Low-power clock distribution networks for 3-D ICs

When the ARM weakly consistent memory model meets speculation: is it necessary?

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Full System Simulation of Many-Core Heterogeneous SoCs using GPU and QEMU Semihosting

A Fully Integrated 0.18-um CMOS Transceiver Chip for X-Band Phased-Array Systems

Effects of Process Variations on 3-D Global Clock Distribution Networks