Concept

Junction Field Effect Transistor

Publications associées (229)

Design of a CNFET Array for Sensing and Control in P450 based Biochips for multiple drug detection

Giovanni De Micheli, Sandro Carrara, Shashi Kanth Bobba

Bio-detection specially dedicated to distributed diagnostics is emerging as a quite important application for Nanobioelectronics. Bio-detection is required to be highly sensitive in order to succeed in sensing small amount of bio-markers in patient’s blood ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2010

TID and Displacement Damage Effects in Vertical and Lateral Power MOSFETs for Integrated DC-DC Converters

Stefano Michelis, Federico Faccio

TID and displacement damage effects are studied for vertical and lateral power MOSFETs in five different technologies in view of the development of radiation-tolerant fully integrated DC-DC converters. Investigation is pushed to the very high level of radi ...

2010

The Effect of Interface Modification on the Properties of Organic Thin-Film Transistors

Franziska Dora Fleischli

In organic thin-film transistors (OTFTs), the conducting channel is located near the interface between the organic semiconductor and the dielectric; this interface is crucial for transistor performance. The goal of this thesis is to study the effect of thi ...

EPFL2010

Silicon nanowires with lateral uniaxial tensile stress profiles for high electron mobility gate-all-around MOSFETs

Mihai Adrian Ionescu, Didier Bouvet, Luca De Michielis, Mohammad Najmzadeh

In this work we present for the first time correlation of lateral uniaxial tensile strain and I–V characteristics of GAA Si NW n-MOSFET, all measured on the same device. Micro-Raman spectroscopy is employed for direct strain measurement on devices to explo ...

Elsevier2010

Offset compensation based on distributed Hall system architecture

Radivoje Popovic, Pavel Kejik

Integrated Hall devices have the great advantage, over other magnetic sensors, that they can be fully fabricated by a standard CMOS process. However they are known to have a relatively large offset (i.e. residual voltage at zero magnetic field). Techniques ...

2010

An experimental investigation of the surface potential in ferroelectric P(VDF-TrFE) FETs

Mihai Adrian Ionescu, Giovanni Antonio Salvatore, Alexandru Rusu

In this paper we report the fabrication and detailed electrical characterization of a ferroelectric transistor (Fe-FET) aiming at the extraction of its physical threshold voltage. The investigated transistors are fabricated on doped bulk silicon with a gat ...

2010

Characterization & Modeling of Gate-Induced-Drain-Leakage with complete overlap and fringing model

Davide Garetto

This paper investigates and models Gate Induced Drain Leakage (GIDL) for a wide variety of high voltage devices with different low doped drain (LDD) structures. Based on TCAD simulations, we propose semi-analytical a pseudo-2D model for Gate induced Drain ...

IEEE Service Center2010

The high-mobility bended n-channel silicon nanowire transistor

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott, Luca De Michielis, Mohammad Najmzadeh

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measur ...

Institute of Electrical and Electronics Engineers2010

Proposal and Performance Analysis of Normally Off n(++) GaN/InAlN/AlN/GaN HEMTs With 1-nm-Thick InAlN Barrier

Nicolas Grandjean, Jean-François Carlin, Eric Feltin, Marcus Gonschorek

Design considerations and performance of n(++) GaN/InAlN/AlN/GaN normally off high-electron mobility transistors (HEMTs) are analyzed. Selective and damage-free dry etching of the gate recess through the GaN cap down to a 1-nm-thick InAlN barrier secures p ...

2010

Analysis of degradation mechanisms in lattice-matched InAlN/GaN high-electron-mobility transistors

Nicolas Grandjean, Jean-François Carlin, Eric Feltin, Marcus Gonschorek

We address degradation aspects of lattice-matched unpassivated InAlN/GaN high-electron-mobility transistors (HEMTs). Stress conditions include an off-state stress, a semi-on stress (with a partially opened channel), and a negative gate bias stress (with so ...

2009

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