Bruit de phase

Résumé

droite|vignette|250x250px| Bruit de phase mesuré par un analyseur de source de signal. L'analyseur montre la partie positive du bruit de phase. Sur cette image, on voit le bruit de phase de la porteuse principale, trois autres signaux et une "colline de bruit". droite|vignette|250x250px| Un signal faible disparaît dans le bruit de phase d'un signal plus fort Dans le traitement du signal, le bruit de phase est la représentation dans le domaine fréquentiel des fluctuations aléatoires de la phase d'une forme d'onde. Il correspond aux écarts dans le domaine temporel par rapport à une périodicité parfaite ("gigue"). En général, les ingénieurs spécialisés en radiofréquences parlent du bruit de phase d'un oscillateur, alors que les ingénieurs spécialisés en systèmes numériques travaillent avec la gigue d'une horloge. Définitions Historiquement, deux définitions contradictoires ont été utilisées pour le bruit de phase. Certains auteurs définissent le bruit de phase comme la dens

Source officielle

https://fr.wikipedia.org/wiki/Bruit_de_phase

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Low power frequency synthesizer for mobile communications systems

Imre Kovacs

A novel frequency synthesizer with a strong emphasis on low-power consumption (2mW) was developed for this thesis. A BAW-resonator was used for the design of the high-frequency oscillator. The BAW's high Q-Factor ensured a minimal power consumption, while providing outstanding phase noise performance. This type of frequency synthesizer can be implemented in practically every mobile wireless system standard, which is relying on batteries as the power supply, such as Bluetooth, Zigbee and others. For this work, a Bluetooth-compatible standard was taken in order to derive the system specifications. The frequency synthesizer then was designed and implemented in a 180nm CMOS process. The approach of the "Sliding-IF" architecture was chosen and modified in order to take full advantage on the BAW oscillator. Therefore a two-stage frequency translation of the signal was necessary, similar to the super-heterodyne transceiver topology. The channel selection and the frequency error correction is done at the second stage, since the BAW-based oscillator does practically not provide any frequency tuning. For this, a Delta-Sigma-Modulator based Fractional-N PLL was developed. A system supply voltage of 1.2V was chosen in order to keep power consumption as low as possible. This supply voltage can also be easily supplied by AA or AAA-batteries and a low-voltage regulator. The most important technique to reduce overall power consumption was to reduce the high-frequency requirements to the system blocks. This was done by modifying the "Sliding-IF" architecture and by the use of the BAW resonator. The minimization of the power consumption required careful choice and design of each of the system blocks. For this, several approaches were analyzed, especially the topology of each block and its optimization were important. A special emphasis on the analysis, design and discussion was also made on the noise, and especially the phase noise. A ring oscillator, a LC-VCO and a BAW-oscillator were implemented and measured in order to validate the theory and the simulation results. The complete frequency synthesizer with an Automatic Amplitude Control, Frequency Dividers, Mixer, Charge-Pump, Phase-Frequency Detector and a Delta-Sigma-Modulator was designed and implemented. This thesis was elaborated in the frame of the MiNAMI and MiMOSA projects of the European research programme (FP6).

EPFL2009

Chargement

Low phase noise, low power CMOS frequency synthesizers for miniature atomic clocks

Yazhou Zhao

EPFL2013

Chargement

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This paper presents a fast and accurate way to design and optimize LC oscillators using the inversion coefficient (IC). This methodology consists of four steps: linear analysis, nonlinear analysis, phase noise analysis, and optimization using a figure of merit. For given amplitude of oscillation and frequency, we are able to determine all the design variables in order to get the best trade-off between current consumption and phase noise. This methodology is demonstrated through the design of Pierce and cross-coupled oscillators and has been verified with BSIM6 metal oxide semiconductor field effect transistor compact model using the parameters of a commercial advanced 40 nm complementary metal oxide semiconductor process.

2015

Chargement

Low power frequency synthesizer for mobile communications systems

Imre Kovacs

EPFL2009