Compatibilité ascendante et descendante

Résumé

vignette|La Wii, qui a succédé à la Gamecube, est compatible avec cette dernière, ce qui en fait un exemple de compatibilité descendante. La rétrocompatibilité, ou compatibilité descendante, est la compatibilité d'un produit vis-à-vis de ses anciennes ou précédentes versions ; la compatibilité ascendante ou postcompatibilité est la compatibilité d'un produit vis-à-vis des versions plus récentes, voire encore en phase de conception. Cette compatibilité peut concerner des appareils ou équipements électroniques, l'univers informatique, des jeux vidéo, des terminaux multimédias reliés ou non à Internet ou encore les logiciels système et les applications. Pour mieux appréhender cette notion, on peut par exemple, faire figurer le produit observé sur une échelle de temps verticale, avec ses versions antérieures en dessous de lui et ses versions postérieures (ou futures) au-dessus de lui ; à partir du produit observé, l'accès aux versions plus anciennes se fait alors en « compatibilité descen

Source officielle

https://fr.wikipedia.org/wiki/Compatibilit%C3%A9_ascendante_et_descendante

À propos de ce résultat

Cette page est générée automatiquement et peut contenir des informations qui ne sont pas correctes, complètes, à jour ou pertinentes par rapport à votre recherche. Il en va de même pour toutes les autres pages de ce site. Veillez à vérifier les informations auprès des sources officielles de l'EPFL.

Publications associées (13)

Publications associées

Chargement

Personnes associées

Chargement

Unités associées

Chargement

Concepts associés (27)

Concepts associés

Chargement

Cours associés (3)

The main objective of the course is to introduce the concept of space system design and engineering. The course will describe the various subsystems involved in the design of a satellite. It will also describe the techniques of systems engineering that are used to obtain a coherent satellite design.

This course teaches the basics of modern software development: designing software, working in a team, writing good code, shipping software, and evolving software. It emphasizes building software that meets high standards of quality, reliability, security, and manageability.

The course teaches non von-Neumann architectures. The first part of the course deals with quantum computing, sensing, and communications. The second focuses on field-coupled and conduction-based nanocomputing, in-memory and molecular computing, cellular automata, and spintronic computing.

Cours associés

Chargement

Séances de cours associées (8)

Séances de cours associées

Chargement

Design and Characterization of a Full-Duplex Multiantenna System for WiFi Networks

Vaneet Aggarwal

In this paper, we present an experiment-and simulation-based study to evaluate the use of full duplex (FD) as a potential mode in practical IEEE 802.11 networks. To enable the study, we designed a 20-MHz multiantenna orthogonal frequency-division-multiplexing (OFDM) FD physical layer and an FD media access control (MAC) protocol, which is backward compatible with current 802.11. Our extensive over-the-air experiments, simulations, and analysis demonstrate the following two results. First, the use of multiple antennas at the physical layer leads to a higher ergodic throughput than its hardware-equivalent multiantenna half-duplex (HD) counterparts for SNRs above the median SNR encountered in practical WiFi deployments. Second, the proposed MAC translates the physical layer rate gain into near doubling of throughput for multinode single-AP networks. The two results allow us to conclude that there are potentially significant benefits gained from including an FD mode in future WiFi standards.

Ieee-Inst Electrical Electronics Engineers Inc2014

Chargement

The aim of this thesis is to understand the dynamics of the growth of catalyst-free III-V semiconductor nanostructures on silicon substrates, focusing the attention mainly on the early stages of growths. A detailed understanding of this first phase of the process is a key step to obtain a completely successful integration of highly functional materials, like the III-Vs, on the CMOS platform, and to synthesize nanostructures with tailored properties. Indeed, the first mandatory step in nanotechnology is the possibility to fabricate nanostructures and nanomaterials, i.e. structures and materials with at least one dimension falling in the nanometer scale. Among different nanostructures, semiconductor nanowires (NWs) have proven to be versatile building blocks for a manifold of applications. In this work two types of nanostructures have been investigated: NWs and V-shaped nanomembranes. Their growth has been performed by molecular beam epitaxy (MBE), a technique that allows to produce ultrapure nanostructures, with very high crystalline quality and atomically sharp interfaces. The growth has been obtained with a self-catalyzed approach, meaning that no external material, apart the constituents of the semiconductor to be grown, has been used. This allows to avoid any possible contamination of the substrate, a fundamental requirement to ensure a full compatibility with the silicon technology. We performed a systematic study on the growth directions of self-catalyzed GaAs NWs grown on silicon substrates. Indeed, when growing III-V NWs on silicon non vertical wires always appear. In order to make NW-based structures on silicon effective for applications like energy harvesting (one of the most promising so far) it is mandatory to control the growth direction and in particular to maximize the yield of NWs perpendicular to the surface. By analyzing the first stages of growth we shed light on the mechanism responsible for the different NWs orientations: we optimized the growth conditions to obtain up to a 100% yield of vertical NWs. Having attained growth of nanostructures in an ordered manner along regular arrays is a subsequent step for the fabrication of devices. In this work our capability to control growth of InAs and GaAs NWs in arrays is presented and the existing challenges for the reproducible growth are highlighted. Lastly, we turned to the growth of nanostructures on exactly oriented (001) substrates, which would make the III-V/group IV integration compatible with the current technological pro- cesses. This led us to the discovery of a new class of III-V semiconductor nanostructures, called V-shaped nanomembranes, characterized by a unique morphology and growth mech- anism and possessing interesting optical properties. An accurate characterization of their morphology and a complete understanding of their nucleation and growth mechanism is reported. These results give a clear pathway of how to obtain fully controlled structures which as such could be useful for the realization of complex branched interconnected nanoelectronic devices.

EPFL2015

Chargement

Ultra-Low-Temperature Silicon and Germanium-on-Silicon Avalanche Photodiodes

Mahdi Aminian

In this thesis we propose the use of photodiodes fabricated in planar technologies to address the detection problem in these applications. A number of solutions exist, optimized for these wavelengths, based on Germanium (Ge) and other III-V materials. In this thesis we focused on Ge thanks to its versatility and ease to use in the clean room. The main advantage of this material is in fact a good compatibility with Silicon and standard CMOS processes. Note that the proposed technology is not based on Silicon/Germanium (SiGe), whereby Ge is used to strain Si to achieve higher bandwidth in Si, not higher sensitivity. In our pure Ge approach, Ge is grafted onto Si (Ge-on-Si), achieving high responsivity at wavelengths of 900nm and higher. The proposed devices can operate in avalanche mode (avalanche photodiodes - APDs), and in Geiger mode (Geiger mode APDs (GAPDs) or single-photon avalanche diodes (SPADs)). To combine the advantages of Ge with single-photon sensitivity and excellent timing resolution of Si-based SPADs, this thesis proposes a new generation of SPADs, achieved in collaboration with Prof. Nanver at TUDelft, aimed at near-infrared range. The fabrication process of the Ge-on-Si SPAD approach, which we are investigating together with the TUDelft group, consists of a standard CMOS process combined with post-processing steps to grow Ge on top of a Si/SiO2 layer. In our study we have investigated the potential for a new generation of massively parallel, Ge-on-Si sensors fabricated in fully CMOS compatible technology. The objective was to address the next challenges of super-parallel pixel arrays, while exploiting the advantages of Ge substrate. The key technology developed in the thesis is a selective chemical-vapor deposition (CVD) epitaxial growth. A novel processing procedure was developed for the p+ Ge surface doping by a sequence of pure-Ga and pure-B depositions (PureGaB). The resulting p+n diodes have exceptionally good I-V characteristics with ideality factor of ~1.1 and low saturation currents. They can be operated both in proportional and in Geiger mode, and exhibit relatively low dark counts. We also looked at techniques to improve red and infrared sensitivity in conventional deep-submicron CMOS processes, by careful selection of standard layers at high depths in the Si substrate. Using the proposed approach, 12 µm-diameter SPADs were fabricated in 0.18µm CMOS technology showing low dark count rates (363 cps) at room temperature and considerably lower rates at cryogenic temperatures (77 K), while the FWHM timing jitter is as low as 76 ps. That of cryogenic SPADs is a novel research direction and in this thesis it was advocated as a significant trend for the future of optical sensing, especially in mid-infrared wavelengths. Low temperature characterizations reported in this thesis exposed how the relevant properties of fabrication materials, such as strength, thermal conductivity, ductility, and electrical resistance are changing. One of the most important properties is superconductivity in materials cooled to extreme temperatures: this is an important trend that will be pursued in the future activities of our group.

EPFL2014

Chargement

Ultra-Low-Temperature Silicon and Germanium-on-Silicon Avalanche Photodiodes

Mahdi Aminian

EPFL2014

EPFL2015