Transistor count | EPFL Graph Search

The transistor count is the number of transistors in an electronic device (typically on a single substrate or "chip"). It is the most common measure of integrated circuit complexity (although the majority of transistors in modern microprocessors are contained in the cache memories, which consist mostly of the same memory cell circuits replicated many times). The rate at which MOS transistor counts have increased generally follows Moore's law, which observed that the transistor count doubles approximately every two years. However, being directly proportional to the area of a chip, transistor count does not represent how advanced the corresponding manufacturing technology is: a better indication of this is the transistor density (the ratio of a chip's transistor count to its area). , the highest transistor count in flash memory was Micron's 2 terabyte (3D-stacked) 16-die, 232-layer V-NAND flash memory chip, with 5.3 trillion floating-gate MOSFETs (3 bits per transistor).

III-V Nanowire Hetero-junction Tunnel FETs integrated on Si

Davide Cutaia

In the last decade the power consumption of electronic devices has increased for both static and active components. Following the Dennard's scaling rule, as long as the transistor sizes are reduced then the supply voltage (VDD) can also be scaled in order to increase the area density and maintain or improve the performances. However, scaling VDD and thus shifting the threshold voltage (Vth) of 60mV in a metal-oxide semiconductor field-effect transistor (MOSFET) increases the OFF state current (Ioff ) by a factor of 10 in the ideal case. The reason for this is that the inverse subthreshold slope (SS) in an ideal MOSFET is limited by the thermionic emission of electrons over a potential barrier, which has an intrinsic physical limit of 60mV/decade. To overcome this limit, novel device concepts have been proposed and the tunnel field-effect transistor (TFET) is one of the most promising because it resembles a MOSFET and should enable to achieve sub-60mV/dec SS, low Ioff and small VDD. The aim of this thesis is to investigate the potential of TFETs by the fabrication and characterization of InAs/Si as p-channel and InAs/GaSb as n-channel device for a complementary TFET technology. III-V nanowires are grown via metal-organic chemical vapor deposition (MOCVD) and are integrated on Si(100) substrates using a novel technique called template-assisted selective epitaxy (TASE), which enables the fabrication of vertical and lateral III-V hetero-structure TFETs. Sub-40nm nanowire cross-section InAs/Si p-TFETs and InAs/GaSb n-TFETs in-plane on Si are demonstrated for the first time. The InAs/Si p-TFETs exhibit state-of-the art performances with an ON state current (Ion) of 4uA/um at VGS=VDS=-0.5V, ON/OFF ratio of 1x10E5 with SSavg of 70-80mV/dec at room temperature. The InAs/GaSb n-TFETs have an order of magnitude larger Ion but the SS is limited by the non-optimized gate-stack on InAs channel and by the depletion of the undoped GaSb source. Different operation regimes of TFETs are investigated by temperature-dependent measurements,Wentzel-Kramers-Brillouin (WKB) modeling and TCAD simulations, indicating that the switching region for InAs/Si is dominated by the presence of traps at the hetero-junction. The abruptness of the band-edges in InAs/GaSb is studied by the extraction of the conductance slope in fabricated p-n and p-i-n tunnel diodes.

EPFL2016

High voltage power supply system for tethered drone part II

Clément Bongini

A high voltage power supply system for a tethered drone is presented. The project is a follow-up to a previous semester project and the purpose of this project is to review the implementation, improve the design and solve problems. The system consists of an inverter part, a transformer part and a rectifier part. The input voltage is 600 VDC and the output voltage is 12VDC for a maximum power of 1500W. The inverter part is composed of 4 transistors controlled by two gate drivers. On the other side of the transformer, we have a bridge rectifier which will be implemented in 3 different ways: a full-bridge diode and two new active rectification systems, including mosfets and controllers. We will first present the different systems chosen, review the previous part and make improvements, then we will implement these new systems, design the prototypes and make tests for each system. Finally, we will test the whole converter.

2021

Conformal Deposition of Conductive Single-Crystalline Cobalt Silicide Layer on Si Wafer via a Molecular Approach

David Baudouin, Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Tsung-Han Lin, Olha Sereda

The realization of metal-semiconductor contacts plays a significant role in ultrascaled integrated circuits. Here, we establish a low-temperature molecular approach for the conformal deposition of a 20-nm Co-rich layer on Si (100) wafers by reaction in solution of Co2(CO)8 with SiH4. Post-annealing at 850 °C under vacuum (~10-5 mbar) yields a crystalline CoSi2 film with a lower surface roughness (Rrms=5.3 nm) by comparison with conventional physical method; this layer exhibiting a metallic conductive behavior (Ohmic behavior) with a low resistivity (ρ =11.6 μΩ.cm) according to four-point probe measurement. This approach is applicable to trench-structured wafers, showing the conformal layer deposition on 3D structures and showcasing the potential of this approach in modern transistor technology.

2018

III-V Nanowire Hetero-junction Tunnel FETs integrated on Si

Davide Cutaia

EPFL2016