Transistor-Transistor logic

Résumé

thumb|Composants TTL thumb| Circuit intégré TTµL-103 de Fairchild (1964) contenant deux portes NON-ET à quatre entrées en logique TTL Transistor-Transistor Logic ou TTL est une famille de circuits logiques utilisée en électronique, inventée en 1961 par sous l'appellation Transistor-Coupled Transistor Logic. De façon indépendante, inspirée par une présentation de la société Fairchild sur les techniques de logique tout-transistor, la société Sylvania a produit les premiers circuits intégrés TTL commerciaux en 1963. Développée et proposée par de nombreux fabricants électroniques, la famille TTL a rapidement constitué une norme de premier plan pour les circuits intégrés utilisés dans les ordinateurs et les appareils numériques. Cette famille emploie une technologie à transistor bipolaire saturé – par opposition aux technologies à transistor bipolaire non saturé ( famille ECL) et à transistor à effet de champ ( familles NMOS, PMOS, CMOS, HCMOS) – distincte des technologies à résistance et

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Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to overcome physical limitations affecting conventional CMOS technology. Here, we propose a novel Schottky barrier device concept based on electrostatic polarity control. Specifically, this device can behave as p- or n-type by simply changing an electric input bias. This device combines More-than-Moore and Beyond CMOS elements to create an efficient technology with a viable path to Very Large Scale Integration (VLSI). This thesis proposes a device/circuit/architecture co-optimization methodology, where aspects of device technology to logic circuit and system design are considered. At device level, a full CMOS compatible fabrication process is presented. In particular, devices are demonstrated using vertically stacked, top-down fabricated silicon nanowires with gate-all-around electrode geometry. Source and drain contacts are implemented using nickel silicide to provide quasi-symmetric conduction of either electrons or holes, depending on the mode of operation. Electrical measurements confirm excellent performance, showing Ion/Ioff > 10^7 and subthreshold slopes approaching the thermal limit, SS ~ 60mV/dec (~ 63mV/dec) for n(p)-type operation in the same physical device. Moreover, the shown devices behave as p-type for a polarization bias (polarity gate voltage, Vpg) of 0V, and n-type for a Vpg = 1V, confirming their compatibility with multi-level static logic circuit design. At logic gate level, two- and four-transistor logic gates are fabricated and tested. In particular, the first fully functional, two-transistor XOR logic gate is demonstrated through electrical characterization, confirming that polarity control can enable more compact logic gate design with respect to conventional CMOS. Furthermore, we show for the first time fabricated four- transistors logic gates that can be reconfigured as NAND or XOR only depending on their external connectivity. In this case, logic gates with full swing output range are experimentally demonstrated. Finally, single device and mixed-mode TCAD simulation results show that lower Vth and more optimized polarization ranges can be expected in scaled devices implementing strain or high-k technologies. At circuit and system level, a full semi-custom logic circuit design tool flow was defined and configured. Using this flow, novel logic libraries based on standard cells or regular gate fabrics were compared with standard CMOS. In this respect, results were shown in comparison to CMOS, including a 40% normalized area-delay product reduction for the analyzed standard cell libraries, and improvements of over 2× in terms of normalized delay for regular Controlled Polarity (CP)-based cells in the context of Structured ASICs. These results, in turn, confirm the interest in further developing and optimizing CP devices, as promising candidates for future digital circuit technology.

EPFL2015

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Leading the Blind

Grace Zgheib

The design and development of innovative FPGA architectures hinge on the flexibility of its toolchain. Retargetable toolchains, like the Verilog-to-Routing (VTR) flow, have been developed to enable the testing of new FPGAs by mapping circuits onto easily-described and possibly theoretical architectures. However, in reality, the difficulty extends beyond having CAD tools that support the architectural changes: it is equally important for FPGA architects to be able to produce reliable delay and area models for these tools. In addition to having acute architectural intuitions, designing and optimizing the circuit at the transistor-level requires architects to have, as well, a particular set of electrical engineering skills and expertise. The process is also painstaking and time-consuming, rendering the comparison of a variety of architectures or the exploration of a wide design space quite complicated and even impossible in practice. In this work, we present a novel approach to model the delay and area of FPGA architectures with various structures and characteristics, quickly and with acceptable accuracy. Abstracting from the user the transistor-level design and optimization that normally accompany the model- ing process, this approach, called FPRESSO, can be used by any architect without prerequisites. We take inspiration from the way a standard-cell flow performs large-scale transistor-size optimization and apply the same concepts to FPGAs, only at a coarser granularity. Skilled designers prepare for FPRESSO a set of locally optimized libraries of basic parameterizable components with a variety of drive strengths. Then, inexperienced users specify arbitrary FPGA architectures as interconnects of these basic components. The architecture is globally optimized, within minutes, through a standard logic synthesis tool, by choosing the most fitting version of each cell and adding buffers wherever appropriate. The resulting delay and area characteristics are automatically returned, in a format suitable for the VTR flow. A correct modeling of any architecture requires not only an optimization of the logic components, but also a proper modeling of the wires connecting these components. This does not only include measuring the length of the wires to determine their respective resistance and capacitance, but also, minimizing their length to reduce the wireload effect on the overall performance. To that end, FPRESSO features an automatic and generic wire modeling approach based on a simulated annealing floorplanning algorithm, to estimate the wires between the different components of the FPGA architecture. To evaluate the results of FPRESSO and confirm the validity of its modeled architectures, we use it to explore a wide range of FPGA architectures. First, we repeat a known study that helped set the standards on the optimal Look-Up-Table (LUT) and cluster size for conventional FPGAs. We show, by comparing with the results of the study, that modeling in FPRESSO preserves the very same trends and conclusions, with significantly less effort. We then extend the search space to cover fracturable LUTs and sparse crossbars, and show how FPRESSO makes the exploration of a huge search space not only possible but easy, efficient, and affordable, for any class of VTR users.

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FinFET integrated low-power circuits for enhanced sensing applications

Antonios Bazigos, Mihai Adrian Ionescu, Paolo Livi, Sara Rigante, Alexandru Rusu

This work presents different circuit architectures that combine sensing and signal readout functions. The basic building block is a Fin Field-Effect Transistor (Fin-FET) used as both sensor and metal gate transistor. Moreover, a hybrid partially gated FinFET is proposed as a unique device enabling the integration of digital gates with biosensing. Each device has been modeled using Verilog-A to explore different designs through Electronic Design Automation (EDA) simulations. A common-source amplifier has been demonstrated to be a simple circuit for the amplification of a threshold voltage shift upon, e.g., a pH change at the sensor surface. Using an enhancement-mode n-MOS transistor as load, an input variation ΔVth ≈ 60 mV/pH can be amplified up to ΔVout ≈ 1 V/pH with good linearity between pH 6 and 10. A depletion-mode n-MOS transistor load has been used to obtain a steeper transition in DC characteristics. By using a hybrid partially gated FinFET as a driving transistor a sensing NOR logic gate has been shown. The use of such hybrid FinFETs allows for building multi-stage circuits. Two examples of such circuits, capable of both sensing and signal conditioning, have been explored and discussed here. The first circuit is a ring oscillator whose oscillating frequency depends on the analyte concentration, i.e., on the voltage drop in the liquid. The second is a pseudo-differential amplifier for differential measurements with tunable gain. The linearity and the sensitivity of the different designs are analyzed for various applications. To the best of our knowledge, no FinFET-based circuits featuring both sensing and readout capabilities have been previously reported.

Elsevier2013

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