Publications associées à Altera

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, Beatrice Shokry Samir Shokry, Wei Hu

Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

2024

A Visionary Look at the Security of Reconfigurable Cloud Computing

Francesco Regazzoni, Mirjana Stojilovic

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Francesco Regazzoni, Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, Ognjen Glamocanin

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

Springer, Cham2023

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Shashwat Shrivastava, Ognjen Glamocanin, Jinwei Yao, Nour Ardo

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Paolo Ienne, Grace Zgheib, Stefan Nikolic

In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer, which moves a carefully selected subset of LUTs from their original positions, so ...

ASSOC COMPUTING MACHINERY2022

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Alexandre Schmid, Lizeth Gonzalez Carabarin

Model compression techniques have lead to a reduction of size and number of computations of Deep Learning models. However, techniques such as pruning mostly lack of a real co-optimization with hardware platforms. For instance, implementing unstructured pru ...

IEEE2022

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

Mirjana Stojilovic, Stefan Nikolic, Morten Borup Petersen

Novel applications have triggered significant changes at the system level of FPGA architecture design, such as the introduction of embedded VLIW processor arrays and hardened NoCs. However, the routing architecture of the soft logic fabric has largely rema ...

2021

Improving First-Order Threshold Implementations of SKINNY

Subhadeep Banik, Andrea Felice Caforio, Ognjen Glamocanin, Daniel Patrick Collins

Threshold Implementations have become a popular generic technique to construct circuits resilient against power analysis attacks.In this paper, we look to devise efficient threshold circuits for the lightweight block cipher family SKINNY. The only threshol ...

Springer, Cham2021

FPGA Architecture: Principles and Progression

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

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Altera

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

A Visionary Look at the Security of Reconfigurable Cloud Computing

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

Improving First-Order Threshold Implementations of SKINNY

FPGA Architecture: Principles and Progression

Graph Chatbot

Chattez avec Graph Search

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Improving First-Order Threshold Implementations of SKINNY

FPGA Architecture: Principles and Progression

A Visionary Look at the Security of Reconfigurable Cloud Computing