Publications associées à Architecture ARM

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both with ...

ASSOC COMPUTING MACHINERY2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as ...

IEEE2020

Plasma-enhanced atomic layer deposition of nickel nanotubes with low resistivity and coherent magnetization dynamics for 3D spintronics

Anna Fontcuberta i Morral, Dirk Grundler, Julien Gay, Simon Robert Escobar Steinvall, Maria Carmen Giordano

We report plasma-enhanced atomic layer deposition (ALD) to prepare conformal nickel thin films and nanotubes by using nickelocene as a precursor, water as the oxidant agent and an in-cycle plasma enhanced reduction step with hydrogen. The optimized ALD pul ...

2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Robert Giterman, Odem Harel

Embedded memories, mostly implemented with static random access memory (SRAM), dominate the area and power of integrated circuits. Gain-cell embedded DRAM (GC-eDRAM) is an alternative to SRAM due to its high density, low power consumption, and two-ported f ...

ELSEVIER SCI LTD2020

REWARD: Design, Optimization, and Evaluation of a Real-Time Relative-Energy Wearable R-Peak Detection Algorithm *

David Atienza Alonso, Jean-Marc Vesin, Lara Orlandic, Sasan Yazdani, Adriana Arza Valdes, Elisabetta De Giovanni

Wearable devices are an unobtrusive, cost-effective means of continuous ambulatory monitoring of chronic cardiovascular diseases. However, on these resource-constrained systems, electrocardiogram (ECG) processing algorithms must consume minimal power and m ...

2019

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

Andreas Peter Burg, David Ruffieux

Microcontroller systems operating at low supply voltage in near- or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power due to the reduced frequency. W ...

IEEE2019

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

David Atienza Alonso, Giovanni Ansaloni, Miguel Peon Quiros, Soumya Subhra Basu, Loris Gérard Duch

Smart edge sensors for bio-signal monitoring must support complex signal processing routines within an extremely small energy envelope. Coarse-Grained Reconfigurable Arrays (CGRAs) are good candidates for tackling these conflicting objectives because, than ...

2019

BLADE: A BitLine Accelerator for Devices on the Edge

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon, Yasir Mahmood Qureshi

The increasing ubiquity of edge devices in the consumer market, along with their ever more computationally expensive workloads, necessitate corresponding increases in computing power to support such workloads. In-memory computing is attractive in edge devi ...

2019

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Architecture ARM

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Energy- and Cost-Efficient VLSI DSP Systems Design with Approximate Computing

Gain-Cell Embedded DRAMs: Modeling and Design Space

Plasma-enhanced atomic layer deposition of nickel nanotubes with low resistivity and coherent magnetization dynamics for 3D spintronics

Gain-Cell Embedded DRAMs: Modeling and Design Space

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

REWARD: Design, Optimization, and Evaluation of a Real-Time Relative-Energy Wearable R-Peak Detection Algorithm *

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

BLADE: A BitLine Accelerator for Devices on the Edge

Graph Chatbot

Chattez avec Graph Search

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Energy- and Cost-Efficient VLSI DSP Systems Design with Approximate Computing

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Plasma-enhanced atomic layer deposition of nickel nanotubes with low resistivity and coherent magnetization dynamics for 3D spintronics

Gain-Cell Embedded DRAMs: Modeling and Design Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

REWARD: Design, Optimization, and Evaluation of a Real-Time Relative-Energy Wearable R-Peak Detection Algorithm *

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

BLADE: A BitLine Accelerator for Devices on the Edge