Concept

Jeu d'instructions x86

Publications associées (35)

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Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Shashwat Shrivastava, Ognjen Glamocanin, Jinwei Yao, Nour Ardo

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

Vishal Gupta

High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequen ...

ASSOC COMPUTING MACHINERY2022

Synthesis of Flexible Accelerators for Early Adoption of Ring-LWE Post-quantum Cryptography

Francesco Regazzoni, Subhadeep Banik, Hamid Nejatollahi

The advent of the quantum computer makes current public-key infrastructure insecure. Cryptography community is addressing this problem by designing, efficiently implementing, and evaluating novel public-key algorithms capable of withstanding quantum comput ...

ASSOC COMPUTING MACHINERY2020

Control-Flow Hijacking attacks are the dominant attack vector against C/C++ programs. Control-Flow Integrity (CFI) solutions mitigate these attacks on the forward edge, i.e., indirect calls through function pointers and virtual calls. Protecting the backwa ...

IEEE COMPUTER SOC2019

Children with hemiplegia have movements' difficulties especially in their upper limbs, these difficulties occur due to the loss of the communication between the brain and the affected side of the body. In this study, visual, audio, and tactile stimulation ...

IEEE2017

This book focuses on the core question of the necessary architectural support provided by hardware to efficiently run virtual machines, and of the corresponding design of the hypervisors that run them. Virtualization is still possible when the instruction ...

Mogan & Claypool2017

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Jeremy Hugues-Felix Constantin

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumpti ...

EPFL2016

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Adam Shmuel Teman, Thomas Christoph Müller, Andrea Bonetti, Jeremy Hugues-Felix Constantin, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

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Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist th ...

2015

Cyme: A Library Maximizing SIMD Computation on User-Defined Containers

Felix Schürmann, Timothée Ewart

This paper presents Cyme, a C++ library aiming at abstracting the usage of SIMD instructions while maximizing the usage of the underlying hardware. Unlike similar efforts such as Boost.simd or VC, Cyme provides generic high level containers to the users wh ...

Springer International Publishing2014