Circuit logique programmable

Résumé

Un circuit logique programmable ou PLD (Programmable Logical Device), est un circuit intégré logique qui peut être programmé après sa fabrication. Il se compose de nombreuses cellules logiques élémentaires contenant des bascules logiques librement connectables. L'utilisateur doit donc programmer le circuit avant de l'utiliser. Les différentes logiques de programmation (unique, reprogrammable) et d'architecture ont conduit à la création de sous-familles dont les plus connues sont les FPGA et les CPLD. Les premiers brevets pour de tels composants datent des années 1980 à 1990 mais c'est au début des années 1990 qu'ils se sont généralisés. Note : La notion de programmation des PLD revient à définir une table de connexion et d'interconnexion des portes logiques. Ce n'est donc pas une programmation algorithmique ( une série d'instructions faite pour tourner sur un processeur) mais une programmation matérielle. Historique & principe Dans les années 1970, le besoin de circuits

Source officielle

https://fr.wikipedia.org/wiki/Circuit_logique_programmable

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A Fast Parallel Matrix Multiplication Reconfigurable Unit Utilized In Face Recognitions Systems

Ioannis Sotiropoulos

In this paper we present a reconfigurable device which significantly improves the execution time of the most computational intensive functions of three of the most widely used face recognition algorithms; those tasks multiply very large dense matrices. The presented architecture utilizes numerous digital signal processing units (DSPs) organized in a parallel manner within a state-of-the-art FPGA device. In order to accelerate those functions we have implemented a "blocked" matrix multiplication algorithm which multiplies certain sub-matrices of fixed-point 32-bit numbers; the size of the sub-matrices has been selected so as to fully exploit the resources of the underlying reconfigurable device. Our system is up to 550 times faster than a conventional general purpose processor when implementing the most CPU intensive parts of a number of very widely used Face Identification Schemes, whereas it is more than 40 times faster than the similar schemes implemented in reconfigurable devices. Moreover, our system is general enough so as to be efficiently utilized in any application incorporating fixed-point matrix multiplications.

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

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Microphone arrays techniques present compelling applications for robotic applications. Those techniques can allow robots to listen to their environment and infer clues from it. Such features might enable capabilities such as natural interaction with humans, interpreting spoken commands or the localization of victims during search and rescue tasks. However, under noisy conditions robotic implementations of microphone arrays might degrade their precision when localizing sound sources. For practical applications, human hearing still leaves behind microphone arrays. Daniel Kisch is an example of how humans are able to efficiently perform echo-localization to recognize their environment, even in noisy and reverberant environments. For ubiquitous computing, another limitation of acoustic localization algorithms is within their capabilities of performing real-time Digital Signal Processing (DSP) operations. To tackle those problems, tradeoffs between size, weight, cost and power consumption compromise the design of acoustic sensors for practical applications. This works presents the design and operation of a large microphone array for DSP applications in realistic environments. To address those problems this project introduces the Pyramic sound capture system designed at LAP in EPFL. Pyramic is a custom hardware which possesses 48 microphones distributed in the edges of a tetrahedron. The microphone arrays interact with a Terasic DE1-SoC board from Altera Cyclone V family devices, which combines a Hard Processor System (HPS) and a Field Programmable Gate Array (FPGA) in the same die. The HPS part integrates a dual-core ARM-based Cortex-A9 processor, which combined with the power of FPGA design suitable for processing multichannel microphone signals. This thesis explains the implementation of the Pyramic array. Moreover, FPGA-based hardware accelerators have been designed to implement a Master SPI communication with the array and a parallel 48 channels FIR filters cascade of the audio data for delay-and-sum beamforming applications. Additionally, the configuration of the HPS part allows the Pyramic array to be controlled through a Linux based OS. The main purpose of the project is to develop a flexible platform in which real-time echo-location algorithms can be implemented. The effectiveness of the Pyramic array design is illustrated by testing the recorded data with offline direction of arrival algorithms developed at LCAV in EPFL.

2016

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Self-replication of complex digital circuits in programmable logic devices

Joël Rossier

Nature is an incredibly complex system resulting from the interactions of many different interdependent species, composed of many individual organisms, which are in turn composed of an extremely large number of cells. In multi-cellular organisms, the parallel operation of millions or trillions of cells is an astounding example of massively parallel processing which results in the emergence of extremely complex global features such as robustness (organisms can tolerate a substantial amount of damage), cicatrization (organisms can self-repair), regeneration (some organisms can regrow certain parts of their bodies), adaptation (through death and replacement of their cells, organisms can cope with a changing environment) and development (organisms grow during their life). Because it underlies these interesting behaviors, multi-cellular organization is a very tempting source of inspiration for the design of artificial systems and a growing number of engineers are beginning to look at it to find inspiration on how to adapt its basic paradigms to electronic computing machines. The POE model defines the three major axes of this bio-inspiration: Phylogenesis (the evolution of the species), Ontogenesis (the development of a complete organism from a single cell as directed by its genetic code), and Epigenesis (the learning processes by interaction with the environment). This thesis aims to contribute to the ontogenetic branch of the POE model through the proposition of different hardware implementations of self-replication strategies that can be integrated in the design of new programmable devices, which in turn could enable structures to replicate within these electronic substrates. To validate the different approaches of self-replication proposed, i.e. construction-based, self-inspection based and self-repairing, each algorithm is applied to a multi-processor system based on the MOVE architecture and implemented in a modified version of the POEtic tissue, a custom programmable device. The different strategies which are proposed could then provide new avenues of exploration for the implementation of bio-inspired systems, for conventional computing systems and, perhaps, even for next-generation electronics based on nanotechnology.

EPFL2008

Chargement

Self-replication of complex digital circuits in programmable logic devices

Joël Rossier

EPFL2008

2016