Logique séquentielle

Résumé

En théorie des circuits électroniques, la logique séquentielle est un type de logique dont les résultats ne dépendent pas seulement des données actuellement traitées mais aussi des données traitées précédemment. Elle s'oppose à la logique combinatoire, dont les résultats sont fonction et seulement fonction des données actuellement traitées. En d'autres termes, la logique séquentielle utilise la notion de mémoire de stockage (Bascules, registres, etc.) alors que la logique combinatoire n'en a pas. L'élément de base de la logique séquentielle est la bascule. Fonctionnements synchrone et asynchrone Dans un système respectant la logique séquentielle, les tâches peuvent être effectuées de deux manières :

fonctionnement asynchrone : dans ce mode de fonctionnement, la sortie logique peut changer d'état à tout moment quand une ou plusieurs entrées changent ;
fonctionnement synchrone : le changement d'état est commandé par un signal d'horloge, les informations évoluent en fonc

Source officielle

https://fr.wikipedia.org/wiki/Logique_s%C3%A9quentielle

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An All-Digital 1.25 Mbps 5-Subcarrier OFDM Backscatter Uplink with Delta-Sigma Modulation for Improved Spurious-Free Dynamic Range

James Daniel Rosenthal

This paper describes an all-digital backscatter modulation approach leveraging delta-sigma modulation (DSM) to improve the in-channel spectral characteristics of orthogonal frequency division multiplexed (OFDM) backscatter communication. We demonstrate through numerical simulations and experimental validation that DSM can improve the spurious-free dynamic range (SFDR) of OFDM subcarriers generated by a low-resolution impedance digital-to-analog converter (DAC), such as an RF switch having two or four different impedance states. We present the design and validation of a prototype OFDM backscatter uplink with DSM implemented with all-digital logic in an FPGA. A single-pole-four-throw CMOS RF switch (i.e. 2-bits of impedance DAC resolution) serves as the backscatter modulator. We experimentally validated the DSM approach with a 2.4 GHz, five-subcarrier OFDM backscatter uplink and a four-times oversampling DSM at up to 1.25 Mbps. In this scenario, the DSM improved the SFDR by 43 dB within the subcarrier band while reducing the overall noise floor in the same band by 11.3 dB. These results confirm that a DSM approach can be used to control quantization noise and improve the spectral characteristics of low-resolution digital impedance modulators for backscatter communication in scenarios where in-channel SFDR is more important than wideband noise performance.

IEEE2022

Chargement

A novel frequency synthesizer with a strong emphasis on low-power consumption (2mW) was developed for this thesis. A BAW-resonator was used for the design of the high-frequency oscillator. The BAW's high Q-Factor ensured a minimal power consumption, while providing outstanding phase noise performance. This type of frequency synthesizer can be implemented in practically every mobile wireless system standard, which is relying on batteries as the power supply, such as Bluetooth, Zigbee and others. For this work, a Bluetooth-compatible standard was taken in order to derive the system specifications. The frequency synthesizer then was designed and implemented in a 180nm CMOS process. The approach of the "Sliding-IF" architecture was chosen and modified in order to take full advantage on the BAW oscillator. Therefore a two-stage frequency translation of the signal was necessary, similar to the super-heterodyne transceiver topology. The channel selection and the frequency error correction is done at the second stage, since the BAW-based oscillator does practically not provide any frequency tuning. For this, a Delta-Sigma-Modulator based Fractional-N PLL was developed. A system supply voltage of 1.2V was chosen in order to keep power consumption as low as possible. This supply voltage can also be easily supplied by AA or AAA-batteries and a low-voltage regulator. The most important technique to reduce overall power consumption was to reduce the high-frequency requirements to the system blocks. This was done by modifying the "Sliding-IF" architecture and by the use of the BAW resonator. The minimization of the power consumption required careful choice and design of each of the system blocks. For this, several approaches were analyzed, especially the topology of each block and its optimization were important. A special emphasis on the analysis, design and discussion was also made on the noise, and especially the phase noise. A ring oscillator, a LC-VCO and a BAW-oscillator were implemented and measured in order to validate the theory and the simulation results. The complete frequency synthesizer with an Automatic Amplitude Control, Frequency Dividers, Mixer, Charge-Pump, Phase-Frequency Detector and a Delta-Sigma-Modulator was designed and implemented. This thesis was elaborated in the frame of the MiNAMI and MiMOSA projects of the European research programme (FP6).

EPFL2009

Chargement

Automated Side-Channel Vulnerability Discovery and Hardening

Ali Galip Bayrak

In traditional cryptography, an attacker tries to infer a mathematical relationship between the inputs and outputs of a cryptosystem to recover secret information. With the advances in the theoretical basis of the cryptographic algorithms, this task became harder and attackers started to seek different approaches. A family of attacks known as side-channel attacks have focused on using information leaked through the underlying device when the cryptographic algorithm is running. For instance, a power analysis attack can exploit the relationship between the inputs of a cryptosystem and the underlying device’s power consumption while performing cryptographic operations on these inputs. Such attacks have shown to be so successful and efficient in practice that prudent designers now insert countermeasures against these attacks to their hardware and software systems. However, the insertion process is challenging to a non-expert in cryptography due to several factors including unnatural structure of the countermeasures (e.g., obfuscating the implementation), use of non-standard elements in the design (e.g., using non-CMOS logic styles), conflict with standard design parameters and the optimization processes of design tools (e.g., adding dummy operations, which are normally eliminated by the design tools to increase performance), etc. To facilitate a reliably-secure design process, this thesis proposes automated methodologies which analyze a given hardware or software cryptosystem and insert appropriate side-channel countermeasures. We first propose one type of hardware countermeasure and show how it can easily be integrated into the standard electronic design automation flow to protect high-level hardware implementations. The countermeasure is based on adding random jitter to the clocks of sequential circuit elements, and incurs a modest area and energy overhead. Next, we propose a hardware extension unit, an instruction shuffler, to existing processors. The unit is very lightweight and does not require any architectural changes, and hence can be used with any processor, increasing the side-channel resistance of the overall system. We then present a compiler, which can easily be combined with the off-the-shelf compilers, to automatically apply countermeasures on given software implementations. We show that the compiler can produce protected implementations that are as efficient as their manually optimized counterparts, eliminating the need for designer expertise and time. Finally, we present an automated security verification methodology, which checks certain properties to detect potential vulnerabilities in a (manually or automatically) protected implementation. Our experiments show that we can successfully detect common security problems in a flawed implementation of a countermeasure within a reasonable amount of time.

EPFL2014

Chargement

EPFL2009

Automated Side-Channel Vulnerability Discovery and Hardening

Ali Galip Bayrak

EPFL2014