Wladyslaw Grabinski

Publications associées (14)

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FOSS EKV2.6 Verilog-A Compact MOSFET Model

Christian Enz, Jean-Michel Sallese, Wladyslaw Grabinski, Eric Vittoz, François Krummenacher, Matthias Bucher, Christophe Lallement

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. T ...

IEEE2019

Analog RF and mm-Wave Design Tradeoff in UTBB FDSOI: Application to a 35 GHz LNA

Jean-Michel Sallese, Wladyslaw Grabinski, Christophe Lallement

The state-of-the art RF and millimeter-wave first-cut circuits design requires simple hand calculation methods to avoid time-consuming iterative simulations. The classical MOSFET sizing methods used in advanced technologies, still rely on questionable and ...

IEEE2018

FOSS EKV 2.6 parameter extractor

Jean-Michel Sallese, Farzan Jazaeri, Wladyslaw Grabinski, Antonios Bazigos, Anurag Mangla, Maria-Anna Chalkiadaki

The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS techno ...

Ieee2015

Compact Modeling of Homojunction Tunnel FETs

Mihai Adrian Ionescu, Wladyslaw Grabinski, Antonios Bazigos, Luca De Michielis, Cem Alper, Arnab Biswas, Nilay Dagtekin

Aggressive scaling of the supply voltage reduces the energy needed for switching of standard CMOS devices. However, advanced CMOS technologies are facing two main problems that consequently lead to higher power consumption: the complexity of a further supp ...

IEEE2014

Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. 1 x 10(19) cm(-3) n-type channel doping, 5-20 nm Si nanowire wi ...

Pergamon-Elsevier Science Ltd2014

Steep slope VO2 switches for wide-band (DC-40 GHz) reconfigurable electronics

Mihai Adrian Ionescu, Andreas Schueler, Antonios Bazigos, Wladyslaw Grabinski, Montserrat Fernandez-Bolanos Badia, Wolfgang Amadeus Vitale, Antonio Paone

IEEE2014

Investigation of Tunnel Field-Effect Transistors as a Capacitor-less Memory Cell

Mihai Adrian Ionescu, Wladyslaw Grabinski, Antonios Bazigos, Arnab Biswas, Nilay Dagtekin

In this work we report experimental results on the use of Tunnel Field-Effect Transistors (TFET) as capacitorless Dynamic Random Access Memory (DRAM) cells, implemented as a double-gate (DG) Fully-Depleted Silicon-On-Insulator (FD-SOI) devices. The devices ...

American Institute of Physics2014

Mobility Extraction Assessment in GAA Si NW JL FETs with Cross-Section Down to 5 nm

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first ...

IEEE2013

A study on 1T Capacitor-less Tunnel FET DRAM Exploiting Ungated Body

Mihai Adrian Ionescu, Wladyslaw Grabinski, Antonios Bazigos, Arnab Biswas, Nilay Dagtekin

IEEE2013

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deple ...

Institute of Electrical and Electronics Engineers2012

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Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

Pergamon-Elsevier Science Ltd2014