Publications de Seniz Esra Küçük

Periodic Structure of Narrow FBARs Operating on SH1 Mode in LN Membrane Solidly Mounted on SiC Substrate

Luis Guillermo Villanueva Torrijo, Seniz Esra Küçük, Nan Xu

We propose a system of narrow FBARs with alternating voltage polarity on top electrodes on the LN platelet and a common bottom floating electrode positioned on a substrate with high acoustic velocity (SiC). This is a YBAR device that is attached to a SiC s ...

Institute of Electrical and Electronics Engineers Inc.2024

Resonance Frequency Dependence Of A1 Lamb Mode On The Pitch Of The Electrode Structure

Luis Guillermo Villanueva Torrijo, Seniz Esra Küçük, Soumya Yandrapalli, Victor Plessky

Dispersion of A1 Lamb mode near onset frequency is discussed. This mode is close to that used in XBAR devices. The typically used approximation is based on elliptic form of slowness curve and ignoring mode interaction is not valid for widely used materials ...

IEEE2021

Thin Film Devices For 5G Communications

Luis Guillermo Villanueva Torrijo, Damien Maillard, Seniz Esra Küçük, Marco Liffredo, Soumya Yandrapalli, Muhammad Faizan

Piezoelectric-based resonators are some of the most used devices in the world. Invisible to most people, they constitute key elements for your mobile phone communications. With the advent of 50, the current technologies for piezoelectric resonators need to ...

IEEE2021

FABRICATION AND ANALYSIS OF THIN FILM LITHUM NIOBATE RESONATORS FOR 5GHz FREQUENCY AND LARGE k(t)(2) APPLICATIONS

Luis Guillermo Villanueva Torrijo, Seniz Esra Küçük, Soumya Yandrapalli, Victor Plessky

This work presents the fabrication and analysis of suspended thin film Lithium Niobate resonators. The yield of the new fabrication process presented below is >90% showing devices with high k(t)(2) of 28% resonators at 5GHz, making them suitable for high f ...

IEEE2021

Copper TSV-Based Process Development for Die-Level Homogeneous and Heterogeneous 3D Integration Platform

Seniz Esra Küçük

Research and development efforts on chip and wafer-scale 3D integration for system miniaturization have been continuing for more than a decade. However, there are still only a handful of 3D integrated products available in the market due to the high cost a ...

EPFL2017

Copper TSV-Based Die-Level Via-Last 3D Integration Process with Parylene-C Adhesive Bonding Technique

Yusuf Leblebici, Seniz Esra Küçük

This paper presents a die-level post-CMOS processing protocol for multi-layer homogeneous 3D integration with adhesive bonding technique using parylene-C as an intermediate bonding layer and sidewall passivation material. This protocol was used to fabricat ...

2016

A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

Seniz Esra Küçük, Yusuf Leblebici, Woo Yeong Cho

In this paper, a die-level CMOS post-processing scheme for 3D integration using the via-last approach is presented for multi-layer stacking. The process includes TSV fabrication, chip-to-chip bonding, and finally the TSV filling with Cu electroplating. The ...

Ieee2016

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Davide Sacchetto, Seniz Esra Küçük, Yusuf Leblebici, Clemens Benedict Nyffeler

In this work, a chip-level post-CMOS processing protocol for 3D integration is presented to achieve multilayer stacking. This protocol includes TSV formation on the top chip, bonding the chips on top of each other, and finally the electrical connection pro ...

2014