Publication

Physically clustered Forward Body Biasing for variability compensation in nano-meter CMOS design

Publications associées (32)

Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design

The evolution and characteristics of the electronics is directly linked to the technological and societal progress. Today, there is a huge variety of electronic solutions offered, with the RF low-power systems, such as wireless sensor networks, wireless bo ...

EPFL2016

An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop

Andreas Peter Burg, Adam Shmuel Teman, Andrea Bonetti

Dual-edge-triggered (DET) synchronous operation is a very attractive option for low-power, high-performance designs. Compared to conventional single-edge synchronous systems, DET operation is capable of providing the same throughput at half the clock frequ ...

2015

Signaling in 3-D integrated circuits, benefits and challenges

Somayyeh Rahimian Omam

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuit ...

EPFL2015

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen

Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, ...

IEEE2014

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen

Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall sili ...

2013

FireBird: PowerPC e200 Based SoC for High Temperature Operation

Andreas Peter Burg, Yusuf Leblebici, Thomas Maeder, Pascal Andreas Meinerzhagen, Conor Joseph Slater, Ömer Cogal, Carl Christian Sten Dominic Senning, Radisav Cojbasic

PowerPC Architecture microcontrollers are commonly used in embedded applications. In this work we present FireBird, the first PowerPC based SoC for reliable operation beyond 200C. It is a significant challenge to design SoCs for reliable operation at high ...

2013

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

Edoardo Charbon, Ties Jan Henderikus Kluter, Claudio Favi, Christian Mester

We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor. In order to save power, data to and from Custom Instruction Units (CIUs) is synchronized via an optical s ...

2012

A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-Vt) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforwar ...

2012

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low power alternatives to con- ventional ...

2012

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