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Reducing leakage in a high-performance deep-submicron instruction cache

Publications associées (117)

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A New Converse Bound for Coded Caching

Michael Christoph Gastpar, Sung Hoon Lim, Chien-Yi Wang

An information-theoretic lower bound is developed for the caching system studied by Maddah-Ali and Niesen. By comparing the proposed lower bound with the decentralized coded caching scheme of Maddah-Ali and Niesen, the optimal memory--rate tradeoff is char ...

2016

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

Multi-Gigabyte On-Chip DRAM Caches for Servers

Dorde Jevdic

While DRAM latency has long been recognized as a major bottleneck in servers, DRAM bandwidth is emerging as an important bottleneck as server processors shift to many-core architectures to allow for sustainable throughput improvements. The rapid expansion ...

EPFL2015

Confluence: unified instruction supply for scale-out servers

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instruction-supply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching tec ...

ACM Press2015

Design of High-Temperature SRAM for Reliable Operation Beyond 250 C

Yusuf Leblebici, Radisav Cojbasic

In this paper, we analyze the 6T SRAM cell failures caused by temperature and supply voltage variations, and we explore the design of robust SRAM cells for high temperature operation. This integral SRAM reliability study is performed using 180nm SOI CMOS p ...

2015

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

Adam Shmuel Teman

As memory density continues to grow in modern systems, accurate analysis of SRAM stability is increasingly important to ensure high yields. Traditional static noise margin metrics fail to capture the dynamic characteristics of SRAM behavior, leading to exp ...

Institute of Electrical and Electronics Engineers2015

Caching (a pair of) Gaussians

Michael Christoph Gastpar, Guillaume Jean Op 't Veld

A source produces i.i.d. vector samples from a Gaussian distribution, but the user is interested in only one component. In the cache phase, not knowing which component the user is interested in, a first compressed description is produced. Upon learning the ...

2015

Information-Theoretic Caching

Michael Christoph Gastpar, Sung Hoon Lim, Chien-Yi Wang

Motivated by the caching problem introduced by Maddah-Ali and Niesen, a problem of distributed source coding with side information is formulated, which captures a distinct interesting aspect of caching. For the single-user case, a single-letter characteriz ...

2015

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology

Davide Sacchetto, Yusuf Leblebici, Jury Sandrini, Tugba Demirci, Maxime Victor Thammasack

This paper presents a read-write design solution for passive ReRAM crossbar memory arrays to overcome the sneak current paths problem. The proposed circuitry includes an auto-calibration feature to overcome the sneak current effects during the READ operati ...

2015

A Primer on Hardware Prefetching

Babak Falsafi

Since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution r ...

Morgan & Claypool2014