Nanogap MEM resonators on SOI | EPFL Graph Search

Today's consumer electronics based on a large variety of time-keeping and frequency reference applications is based on quartz-crystal oscillators, because of their excellent performances in terms of quality factor, thermal and frequency stability. However, macroscopic size and CMOS incompatibility of quartz-crystal resonators draw a major limit on the miniaturization of wireless communication applications. For this reason, silicon microelectromechanical (MEM) resonators are considered promising candidates to replace quartz-oscillators in VLSI communication systems, due to their compactness, design flexibility and CMOS process compatibility. This work reports on the design, fabrication and characterization of MEM bulk lateral resonators with resonance frequencies in the order of tens of MHz. The need of stable, low cost and high yield processes for fabricating devices with extremely narrow (sub 100 nm) transduction gaps is a main research driver, together with the requirements of improved designs which include high quality factors and appropriate power handling. We are investigating two major designs: (1) longitudinal beam resonators and (2) novel fragmented-membrane resonators that respond to both high quality factor (Q) and low motional resistance (Rm) requirements. We propose several design optimizations for solving some of the issues which currently affect the MEM resonator performance, like the frequency stability and Q enhancement through energy loss minimization. An original fabrication process is presented, which enables the manufacturing of SOI-based, fully monocrystalline devices with 100 nm transduction gaps and aspect ratios as high as [60:1], without the need of advanced lithography techniques. We successfully validate the fabrication process on two different SOI substrates, with silicon film thicknesses of 1.5 µm and 6.25 µm. This thickness range combined to the doping level corresponds to partially depleted SOI, which can be a substrate of choice for the fabrication of future integrated hybrid MEMS-CMOS integrated circuits for communication applications. The fabricated structures are successfully characterized, demonstrating excellent resonator performance at room temperature. Q's as high as 235'000 and Rm's as low as 59 kΩ have been extracted in vacuum. Atmospheric pressure frequency response measurements of the fragmented membrane resonators show Q's of 3'600. This value is among the best reported to date, opening the possibility for atmospheric pressure applications such as mass-detection for gas sensing applications with detection done without a special package, just by direct exposure of the resonator to the environment. A novel study on temperature dependence (between 80 K and 320 K) of the fragmented membrane resonators is presented and discussed. Significant Q increase and Rm reduction are experimentally observed at cryogenic temperatures. The bulk mode resonators developed and discussed in this thesis can successfully be integrated in oscillator circuits, as we demonstrate by simulating a Pierce topology based on the calibrated equivalent circuit model of a 24.48 MHz fragmented membrane BLR. Our oscillator shows very good phase-noise performance of -142 dBc/Hz at 1 kHz offset from the carrier and the noise floor at -144 dBc/Hz, which nearly meets the GSM specifications.

Development of Lamb wave resonators in thin film X-cut lithium niobate

Muhammad Faizan

Microelectromechanical systems (MEMS) is among the most revolutionary technologies of 21st century, with the applications ranging from industrial systems to consumer electronics. Using MEMS in battery-powered wireless devices has long been seen as the evolutionary step in achieving a highly miniaturized and efficient RF frontend (RFFE) for the next generation of communication systems. Piezoelectric MEMS resonators are the essential component of every RFFE as they do a phenomenal job of frequency generation and filtering while meeting the stringent specifications regarding power budget and form factor. This thesis focuses on the design, fabrication and characterization of Lamb wave resonators on thin film LN for RF filters and oscillators. The goal of the project is to improve the electromechanical coupling (k_t^2) and quality factor (Q) of the resonators by first selecting an appropriate LN cut and in-plane device orientation for the intended mode and secondly, by optimizing different geometrical parameters such as electrode coverage (duty factor), gap, bus and anchor dimensions. With the goal to improve k_t^2 of the resonator, we fabricate devices with varying electrode coverages from 20% to 70% for Al and Pt electrodes. Our results show that low electrode coverages (20% to 40%) do not have significant effect on k_t^2, but for higher electrode coverages (> 40%), k_t^2 reduces by ~35% due to the non-linear increase in static capacitance (C_o). The electrode material does not show any significant dependence on k_t^2 but devices with Al electrodes show larger Q (in our case x2) than devices with Pt electrodes due to higher resistive losses. We demonstrate devices with the highest reported k_t^2 of 31% and 40% for S0 and SH0 mode resonators with Q of 720 and 590, operating at around 500 MHz and 300 MHz, respectively, in X-cut LN. In our next effort to further enhance Q, we fabricate devices by varying the geometrical dimensions of different inactive region elements such as anchor, bus and gap of the resonator. Each element plays a very important role in containing energy within the resonator cavity resulting in Q improvement. Our measurements suggest that a square anchor (L_a=W_a), a wider bus (W_b>0.3Î») and a longer gap (g=2Î») helps to improve Q of the resonator. The highest Q of 1900 and k_t^2 of 41% is achieved for the design parameters of g=2Î», W_b= 3Î»/4, W_a= 3Î»/4 and L_a= 3Î»/4, resulting in the highest-ever achieved Figure-of-Merit (FoM) of 780 for SH0 mode resonators in X-cut LN. We also demonstrated the fabrication of high performance A1 mode resonator operating in 3-6 GHz range in Z-cut LN. Our fabricated devices exhibit k_t^2 and Q up to 28% and 300, respectively. This performance is in agreement with the FEM simulations and is suitable for the 5G RF-filter technology. Lastly, we use 2-port SH0 mode resonators to build oscillators and measure phase noise (PN) as it directly relates to its frequency stability. We investigate the dependence of PN on carrier power, Q and k_t^2 by measuring the PN for 60 oscillators using different SH0 mode resonators. Our results show that a higher carrier power and Q significantly reduces PN and improves frequency stability of the oscillator, whereas k_t^2 does not show significant influence on PN. We achieve a low phase noise of -96 dBc/Hz and -129 dBc/Hz, at the offset frequency of 1 kHz and 10 kHz, respectively, for the resonator with Q of 2500.

EPFL2021

Encapsulated Low Frequency Vibrating Body Field Effect Resonator

Marion Hermersdorf

Resonators for time and frequency reference applications are essential elements found in most electronic devices surrounding us. The continuous minimization and ubiquitous distribution of such electronic devices and circuits demands for resonators of smaller size, lower cost, and reduced power consumption. Micro-electro-mechanical (MEM) resonators have the potential to replace the widely used quartz resonators, which are relative large and difficult to integrate with electronic circuits. The MEM resonators can be CMOS compatible, smaller in size, and therefore cheaper than quartz resonators, while providing similar performance characteristics. The required hermitic encapsulation of the MEM resonator at a low pressure and in a clean environment, has been the dominant bottle-neck on their path to successful commercialisation. In this work, the development, fabrication, and characterization of an encapsulated low frequency MEM resonator, based on the vibrating body field effect transistor (VB-FET), is presented. This in-plane flexural mode resonator was designed for a resonance frequency of 262 kHz, and fabricated on a silicon-on-insulator (SOI) wafer. The VB-FET provides a higher signal gain and lower motional resistance compared to other electro-mechanical transducers. A thin film encapsulation process was developed for the wafer level packaging of the resonators. In two fabrication runs the VB-FET resonators were fabricated with 150 nm to 400 nm wide trenches at the gate and drive electrodes using ebeam lithography. Two ion implantations realized the n-type channel enhancement FET on the vibrating structure, and the p-type gate on the non-vibrating structures. A quality factor for up to 12,000 was measured with resonance frequencies around 210 kHz, and a temperature dependency of the frequency of -850 ppm/K. Losses at the anchor points, intrinsic stress in the resonator's body, and stress induced by the thermal gate oxide are explanations for this low performance. With the gate bias voltage a tuning of the resonance frequency of up to 5.2 kHz/V was possible. A motional resistance down to 1 kΩ was measured. Pressure dependent measurement showed that significant air damping occurs at 1 Pa for this resonator. A thin film encapsulation process was developed for the VB-FET MEM resonator based on sacrificial polysilicon and a silicon oxide cap. In numerous tests, individual encapsulation process steps were optimized. Arrays of submicron trenches in the encapsulation cap were used for release etching the sacrificial polysilicon. A sputtered silicon oxide layer closed these release etch trenches with minimal contamination inside the cavity. Cavities spanning 45 μm in width and more than 70 μm in length were successful fabricated. Although, the final encapsulation of the MEM resonators showed a breaking of the silicon oxide cap and a contamination by the sealing polysilicon. No functional encapsulated resonators could be measured. The novelty of this work is the fabrication of a VB-FET MEM resonator with a resonance frequency lower than 300 kHz, which held certain fabrication challenges. Also, the thin film encapsulation process using submicron etch release trenches and sacrificial polysilicon has not been report before. Based on the documented measurement results, further investigations and optimizations regarding the resonator design could result in a considerable improvement of the resonator's performance. The developed thin film encapsulation process requires assumingly only a small modification to produce a functional encapsulation. Provided a sufficient pressure level can be achieved inside the cavity, this encapsulation process could be applied to other resonators and MEMS structures, which have a silicon oxide surface layer.

EPFL2013

In-IC Strategies for 3D Devices in Bulk Silicon

Matthieu Bopp

The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law during more than 40 years. Today the traditional scaling has reached limits when physical phenomena inherent to the nanoscale generate as many challenges and issues as the gain in performance compared to previous device generation. This work proposes another alternative to overcome the difficulty of traditional scaling and still continue to increase the integration density and with improved device performances: the vertical stacking of devices or the completion of the planar integration with an in-volume, vertical integration of multiple channels and other structures. In contrast with many other works, we investigated stacking of channel on bulk silicon substrates which will avoid the higher costs of engineered substrates like SOI. This thesis reports on the development of strategies to fabricate advanced multilevel 3D structures in bulk silicon, and their integration as stacked transistor channels. We propose some credible alternatives for the design, fabrication and characterization of a Field Effect Transistor exploiting vertically stacked channels. We investigate two main technologies: (i) silicon transformation during a high temperature annealing in hydrogen ambient, and, (ii) profile engineered trenches. We propose several design and process optimization to be able to fabricate stacked silicon structures (membranes, nanowires, Fins) that could be used as suspended transistor channels. Two original fabrication processes are presented, enabling the manufacturing of bulk silicon transistors with a matrix of stacked channels. We successfully validate the fabrication process of two level suspended Fin channel transistor. Double-stacks of nanowires stacks (promoting a new concept of stacking the stacks) are also demonstrated morphologically. Some of the fabricated structures are electrically characterized, demonstrating basic functionally of a MOSFET but also some difficult control of parasitic transistor effect. We have tried to eliminate such effects by a special design of the source and drain pads in a second integration process. The transfer, Id-Vg, and output, Id-Vd, characteristics of fabricated devices always show a transistor behavior and the extracted mobility values for n-type transistors tend to confirm that the conduction in the suspended channels dominates over the sidewall or bottom parasitic transistor. However, the presence of a parasitic transistor remains important and its elimination needs further efforts. The demonstrated 3D silicon structures in this work show the possibility to sculpture and integrate stacked channels in bulk silicon for making MOSFETs with multiple suspended channels, potentially with independently control of these channels. The morphological work carried out can also find novel applications in other silicon applications areas, like photonics, micro fluidics and Micro-Electro-Mechanical-Systems.

EPFL2011