High-precision DAC based on a self-calibrated sub-binary radix converter
Graph Chatbot
Chattez avec Graph Search
Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.
AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.
During the last decades, the usage of silicon photodetectors, both as stand-alone sensor or integrated in arrays, grew tremendously. They are now found in almost any application and any market range, from leisure products to high-end scientific apparatuses ...
As CMOS processes continue to scale to smaller dimensions, the increased fT of the devices and smaller parasitic capacitance allow formore power efficient and faster digital circuits to be made. But at the same time, output impedance of transistors has gon ...
A 0.88 mm 2 65-nm analog-to-digital converter (ADC)-based serial link transceiver is designed with a maximum-likelihood sequence detector (MLSD) for robust equalization. The MLSD is optimized in a pipelined look-ahead architecture to reach 10 Gb/s at 5.8 p ...
In this Letter, a direct light-to-digital converter based on an MOS-PN photodetector driven by pulsed voltage is presented. The objective is to avoid any analog-to-digital or time-to-digital conversion and, thereby, to pave the way for a new generation of ...
This paper presents the design and implementation of a 46-kS/s CMOS switch-capacitor dual-mode capacitive sensor interface circuit for inkjet-printed capacitive humidity sensors. The specifications of the interface circuit, which includes a capacitance-to- ...
Institute of Electrical and Electronics Engineers2015
This thesis describes a novel digital background calibration scheme for pipelined ADCs with nonlinear interstage gain. Errors caused by the nonlinear gains are corrected in real-time by adaptively post-processing the digital stage outputs. The goal of this ...
The long-standing analog-to-digital conversion paradigm based on Shannon/Nyquist sampling has been challenged lately, mostly in situations such as radar and communication signal processing where signal bandwidth is so large that sampling architectures cons ...
The demand for high-quality and high-speed imaging has increased. Column-parallel ≥14b A/D conversion is one of the major approaches to meet these requirements in CMOS image sensors (CIS). Oversampling ADCs such as incremental delta-sigma (I-ΔΣ) ADCs are t ...
A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of c ...
In a nonideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used in an analog-to-digital converter (ADC), it injects the spurious tones into the sampled data. These distortions ...