Design and Exploration of Low-Power Analog to Information Conversion Based on Compressed Sensing

The long-standing analog-to-digital conversion paradigm based on Shannon/Nyquist sampling has been challenged lately, mostly in situations such as radar and communication signal processing where signal bandwidth is so large that sampling architectures constraints are simply not manageable. Compressed Sensing (CS) [1], [2], [3] is a new emerging signal acquisition/compression paradigm that offers a striking alternative to traditional signal acquisition. CS states that a signal having a sparse representation in some dictionary of waveforms can be recovered from a small number of linear projections of that signal, thus enabling efficient sensing, sampling and compression. Interestingly, by merging the sampling and compression steps, CS also removes a large part of the digital architecture and might thus considerably simplify analog-to-information (A2I) conversion devices. This so-called ”analog CS”, where compression occurs directly in the analog sensor readout electronics prior to analog-to-digial conversion, could thus be of great importance for applications where bandwidth is moderate, but computationally complex, and power resources are severely constrained. A promising example is embedded e-health monitoring devices, which must precisely operate in these conditions. Unfortunately, there are very few system wide implementations of CS including an analog front-end that could serve as reference design for these applications. In our previous work [4], we quantified and validated the potential of digital CS systems for real-time and energy-efficient electrocardiogram (ECG) compression on resource-constrained sensing platforms. In this paper, we review the state-of-the-art implementations of CS-based signal acquisition systems and perform a complete system level analysis for each implementation to highlight their strengths and weaknesses regarding implementation complexity, performance and power consumption. Then, we introduce the Spread Spectrum Random Modulator Pre-Integrator (SRMPI), which is a new design and implementation of a CS based A2I read-out system that uses spread spectrum techniques prior to random modulation in order to produce the low rate set of digital samples. Finally, we experimentally built an SRMPI prototype to compare it with state-of-the-art CS-based signal acquisition systems, focusing on critical system design parameters and constraints, and show that this new proposed architecture offers a compelling alternative, in particular for low power and computationally-constrained embedded systems.