0.35 μm 22μW Multiphase Programmable Clock Generator for Circular Memory SC FIR Filter For Wireless Sensor Applications

Rafal Tomasz Dlugosz
2006
Article de conférence

The paper presents the programmable multiphase clock generator for switched-capacitor finite impulse response (SC FIR) circular memory filters. The proposed programmable clock circuit enables easy division of such kind of filters into different orders smaller sections, which when connected in series, lead to increase in filter efficiency: reduction of chip area, power dissipation, and rising up of the speed. The proposed clock generator enables adjustment of the impulses width, that simplifies design process and leads to structure, which is more robust to process variation. The clock circuit realized in CMOS 0.35μm technology, dissipates 22 μW from 2 V power supply.

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Rafal Tomasz Dlugosz
2006
Article de conférence

Résumé

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https://infoscience.epfl.ch/record/167732?ln=fr

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Ultra Low Power Switched Current Finite Impulse Response Filter Banks Realized in CMOS 0.18 um technology

Rafal Tomasz Dlugosz

Ultra low power circuits are in high demand in many applications especially in wireless sensor networks (WSN), where energy is scavenged from environment. WSN systems contain different blocks, such as: sensors, filters, analog-to-digital converters, very often a simple processor and the RF front end block. This paper concerns ultra low power finite impulse response (FIR) filters and filter banks implemented in a switched current (SI) technique. In this paper new SI FIR filter structures and filter banks have been proposed. These circuits operate in the current mode and do not use operational amplifiers, what enables very low power dissipation on the level of several μW. Proposed filters incorporate transistors working under threshold level for the voltage supply that is in the range 0.5 – 0.7 V. The simulated attenuation in the stopband of the frequency response is limited to about 45 dB, what is due to different nonidealities, but such value is usually sufficient in WSN applications. The SI technique features many interesting mechanisms that simplify realization of analog filter banks. The signal samples that are stored in the delay lane are in SI filters copied to the filter coefficients using current mirrors. As a result, there exists the possibility to connect many sets of filter coefficients to a single delay line without the speed limitation. Ultra low power operation of proposed filters is also possible due to a special structure of the clock generator that only consists from switches and NOT gates.

2007

Chargement

Power and Area Efficient Circular-Memory Switched-Capacitor FIR Baseband Filter for WCDMA/GSM

Rafal Tomasz Dlugosz

This paper presents a new two-sections architecture of a low power switched capacitor (SC) finite impulse response (FIR) filter suitable for base-band signal processing in WCDMA and in GSM standards. The low power operation is possible due to several optimization techniques like division of the filter into shorter sections and by use a low power control logic block. The important advantage is possibility of using filter with the same coefficients in both standard modes. The only difference is in the sampling frequency (fS). Our proposed programmable 24-taps FIR filter dissipates 4.5 mW of power from the 1.8 V power supply for fS = 20 MHz. Controlling the supply voltage allows for control of both the fS and the power dissipation.

2008

Chargement

Design and Optimization of Operational Amplifiers for SC Systems - a Comparative Study in CMOS 0.8 μm, 0.35 μm, 0.18 μm Technologies

Rafal Tomasz Dlugosz

Design and optimization of a simple but efficient operational amplifier (OA) for switched-capacitor finite impulse response (SC FIR) filters are presented. The main design criteria are: proper characteristics for application in SC FIR filters, simplicity of the circuit structure, the area in the silicon realization and low power dissipation. The OAs have been realized in three different CMOS technologies, namely AMS 0.8 μm and 0.35 μm as well as TSMC 0.18 μm, for comparison. The best performance has been achieved in the 0.18 μm process, as expected. The gain bandwidth product (GBP) equals 1.9 GHz in this case, while the power dissipation 700 μW at 1.8V power supply. The chip area equals 280 μm2 that is 40 times less than in case of the 0.8 μm process.

2009

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