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A new single-photon avalanche diode in 90nm standard CMOS technology

Publications associées (35)

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Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

Alexandre Schmid, Seyed Armin Tajalli, Mahsa Shoaran, Yusuf Leblebici

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits ...

2015

Ultra-Low-Temperature Silicon and Germanium-on-Silicon Avalanche Photodiodes

Mahdi Aminian

In this thesis we propose the use of photodiodes fabricated in planar technologies to address the detection problem in these applications. A number of solutions exist, optimized for these wavelengths, based on Germanium (Ge) and other III-V materials. In t ...

EPFL2014

A Geiger Mode APD fabricated in Standard 65nm CMOS Technology

Edoardo Charbon, Hyungjune Yoon

We present the first avalanche photodiode (APD) successfully fabricated in standard 65nm CMOS technology. The APD operates both in proportional and Geiger mode at -60C to +60C temperature range. The device comprises an octagonal n+p-well junction surrounde ...

2013

Single-layer MoS₂

Branimir Radisavljevic

This thesis explores the electronic properties of one layered transition-metal dichalcogenide – single-layer MoS2, and demonstrates the first transistors and integrated circuits with characteristics that outperform graphene electronics in many aspects and ...

EPFL2013

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

Ferroelectric Field Effect Transistor for Memory and Switch Applications

Giovanni Antonio Salvatore

Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid appro ...

EPFL2011

Single-photon Avalanche Diodes in sub-100nm Standard CMOS Technologies

Edoardo Charbon, Hyungjune Yoon, Mohammad Azim Karami

Single-photon avalanche diodes (SPADs) are evaluated in two sub-100nm CMOS technologies. Several geometries are implemented, whereas premature edge breakdown (PEB) prevention is achieved with n-well rings. The octagonal SPADs are implemented in 90nm and 65 ...

2011

Integration of Engineered Source and Drain Extensions in Double Gate Mosfet with Sub-32nm Channel Length

Jyotshna Bhandari

Since the advent of CMOS technology, the semiconductor industry has been successful in achieving continuously improved performance. The feature size of the most important electronic device, the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), ha ...

EPFL2011

Process Variation and Leakage Power

Bahman Kheradmand Boroujeni

Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...

EPFL2011

Microelectronics Meets Biology

Emile Dupont

Microfluidics plays a key role in the design of automated platforms for realizing biological assays in a miniaturized format. Several advantages are offered by a microfluidic system, namely, low sample and reagent consumption (typically a few microliters), ...

EPFL2010