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Towards Multi-Fabric 3D Integration Architectures

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Towards Multi-Fabric 3D Integration Architectures

Graph Chatbot

Chattez avec Graph Search

DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric

Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Near-Memory Data Services

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Method for speeding up boolean satisfiability

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Single-FPGA, Scalable, Low-Power, and High-Quality 3D Ultrasound Beamformer

Method for speeding up boolean satisfiability

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers

DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Near-Memory Data Services

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Single-FPGA, Scalable, Low-Power, and High-Quality 3D Ultrasound Beamformer