Cycles per instructionIn computer architecture, cycles per instruction (aka clock cycles per instruction, clocks per instruction, or CPI) is one aspect of a processor's performance: the average number of clock cycles per instruction for a program or program fragment. It is the multiplicative inverse of instructions per cycle. The average of Cycles Per Instruction in a given process (CPI) is defined by the following weighted average: Where is the number of instructions for a given instruction type , is the clock-cycles for that instruction type and is the total instruction count.
Comparison of instruction set architecturesAn instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost (among other things); because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA.
POWER8thumb|2 processeurs 6 cores Power8 montés sur un Dual Chip Module (DCM) Le POWER8 est un processeur de la gamme POWER conçu et produit par IBM et annoncé en . Il est gravé en technologie 22 nm, avec une fréquence d'horloge maximum de 4,15 GHz. Une des principales nouveautés annoncées par IBM est la possibilité offerte à des tiers fabricants de composants d'ajouter des éléments dans la nouvelle génération de serveurs à base de POWER8, en particulier en partenariat avec Google.
Instruction unitThe instruction unit (I-unit or IU), also called, e.g., instruction fetch unit (IFU), instruction issue unit (IIU), instruction sequencing unit (ISU), in a central processing unit (CPU) is responsible for organizing program instructions to be fetched from memory, and executed, in an appropriate order, and for forwarding them to an execution unit (E-unit or EU). The I-unit may also do, e.g., address resolution, pre-fetching, prior to forwarding an instruction. It is a part of the control unit, which in turn is part of the CPU.
Bulldozer (microarchitecture)La microarchitecture Bulldozer d'AMD, commercialisée à partir de 2011, fait suite à la microarchitecture K10 introduite fin 2007. Les processeurs l'utilisant seront d'abord gravés en . Nouvelle organisation des cœurs : AMD fusionne deux cœurs en un « module », une architecture entre double cœur et SMT (simultaneous multithreading). Une partie des composants sont mutualisés (les unités de calcul sur entiers passent de 3 par cœur K10 à 4 par module Bulldozer, l'unité de calcul en virgule flottante est utilisable par tous les threads d'un module, le cache mémoire de niveau 2 et d'autres composants sont communs).
Instruction cycleThe instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch-execute cycle) is the cycle that the central processing unit (CPU) follows from boot-up until the computer has shut down in order to process instructions. It is composed of three main stages: the fetch stage, the decode stage, and the execute stage. In simpler CPUs, the instruction cycle is executed sequentially, each instruction being processed before the next one is started.
Supercomputer architectureApproaches to supercomputer architecture have taken dramatic turns since the earliest systems were introduced in the 1960s. Early supercomputer architectures pioneered by Seymour Cray relied on compact innovative designs and local parallelism to achieve superior computational peak performance. However, in time the demand for increased computational power ushered in the age of massively parallel systems.
Prefetch input queueFetching the instruction opcodes from program memory well in advance is known as prefetching and it is served by using a prefetch input queue (PIQ). The pre-fetched instructions are stored in a queue. The fetching of opcodes well in advance, prior to their need for execution, increases the overall efficiency of the processor boosting its speed. The processor no longer has to wait for the memory access operations for the subsequent instruction opcode to complete. This architecture was prominently used in the Intel 8086 microprocessor.
Zero ASICZero ASIC Corporation, formerly Adapteva, Inc., is a fabless semiconductor company focusing on low power many core microprocessor design. The company was the second company to announce a design with 1,000 specialized processing cores on a single integrated circuit. Adapteva was founded in 2008 with the goal of bringing a ten times advancement in floating-point performance per watt for the mobile device market.
Pentium ProLe Pentium Pro est un microprocesseur x86 32 bits produit par Intel, de sixième génération (architecture P6), sorti en 1995. Avec ce processeur, Intel s'est attaqué au marché des serveurs pour entreprises, dominé par IBM, faisant baisser le prix des serveurs et monter en puissance les architectures Intel, ce qui profite aussi aux produits pour PC, devenus assez puissants pour traiter de grandes quantités de sons et photos. Ce processeur a été conçu pour les systèmes 32 bits de l'époque comme Windows NT et OS/2.
