Memristive Biosensors Under Varying Humidity Conditions

Camilla Baj-Rossi, Sandro Carrara, Akshat Dave, Giovanni De Micheli, Yusuf Leblebici, Francesca Puppo, Davide Sacchetto
Institute of Electrical and Electronics Engineers, 2014
Article

Résumé

We attempt to examine the potential of silicon nanowire memristors in the field of nanobiosensing. The mem- ristive devices are crystalline Silicon (Si) Nanowires (NWs) with Nickel Silicide (NiSi) terminals. The nanowires are fabricated on a Silicon-on-Insulator (SOI) wafer by an Ebeam Lithography Technique (EBL) process that allows high resolution at the nanoscale. A Deep Reactive Ion Etching (DRIE) technique is used to define free-standing nanowires. The close alignment between Silicon (Si) and Nickel-Silicide (NiSi) terminals forms a Schottky- barrier at their junction. The memristive effect of the fabricated devices matches well with the memristor theory. An equivalent circuit reproducing the memristive effect in current-voltage (I- V) characteristics of our silicon nanowires is presented too. The memristive silicon nanowire devices are then functionalized with anti-human VEGF (Vascular Endothelial Growth Factor) antibody and I-V characteristics are examined for the nanowires prior to and after protein functionalization. The uptake of bio- molecules linked to the surface of the memristive NWs is con- firmed by the increased voltage gap in the hysteresis curve. The effects of varying humidity conditions on the conductivity of bio- modified memristive silicon nanowires are deeply investigated

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https://infoscience.epfl.ch/record/191233?ln=fr

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Camilla Baj-Rossi, Sandro Carrara, Akshat Dave, Giovanni De Micheli, Yusuf Leblebici, Francesca Puppo, Davide Sacchetto
Institute of Electrical and Electronics Engineers, 2014
Article

Résumé

Official source

https://infoscience.epfl.ch/record/191233?ln=fr

À propos de ce résultat

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Concepts associés

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Publications associées (11)

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Publications associées (11)

The aim of this thesis is to understand the dynamics of the growth of catalyst-free III-V semiconductor nanostructures on silicon substrates, focusing the attention mainly on the early stages of growths. A detailed understanding of this first phase of the process is a key step to obtain a completely successful integration of highly functional materials, like the III-Vs, on the CMOS platform, and to synthesize nanostructures with tailored properties. Indeed, the first mandatory step in nanotechnology is the possibility to fabricate nanostructures and nanomaterials, i.e. structures and materials with at least one dimension falling in the nanometer scale. Among different nanostructures, semiconductor nanowires (NWs) have proven to be versatile building blocks for a manifold of applications. In this work two types of nanostructures have been investigated: NWs and V-shaped nanomembranes. Their growth has been performed by molecular beam epitaxy (MBE), a technique that allows to produce ultrapure nanostructures, with very high crystalline quality and atomically sharp interfaces. The growth has been obtained with a self-catalyzed approach, meaning that no external material, apart the constituents of the semiconductor to be grown, has been used. This allows to avoid any possible contamination of the substrate, a fundamental requirement to ensure a full compatibility with the silicon technology. We performed a systematic study on the growth directions of self-catalyzed GaAs NWs grown on silicon substrates. Indeed, when growing III-V NWs on silicon non vertical wires always appear. In order to make NW-based structures on silicon effective for applications like energy harvesting (one of the most promising so far) it is mandatory to control the growth direction and in particular to maximize the yield of NWs perpendicular to the surface. By analyzing the first stages of growth we shed light on the mechanism responsible for the different NWs orientations: we optimized the growth conditions to obtain up to a 100% yield of vertical NWs. Having attained growth of nanostructures in an ordered manner along regular arrays is a subsequent step for the fabrication of devices. In this work our capability to control growth of InAs and GaAs NWs in arrays is presented and the existing challenges for the reproducible growth are highlighted. Lastly, we turned to the growth of nanostructures on exactly oriented (001) substrates, which would make the III-V/group IV integration compatible with the current technological pro- cesses. This led us to the discovery of a new class of III-V semiconductor nanostructures, called V-shaped nanomembranes, characterized by a unique morphology and growth mech- anism and possessing interesting optical properties. An accurate characterization of their morphology and a complete understanding of their nucleation and growth mechanism is reported. These results give a clear pathway of how to obtain fully controlled structures which as such could be useful for the realization of complex branched interconnected nanoelectronic devices.

EPFL2015

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Lateral Strain Profile as Key Technology Booster for All-Silicon Tunnel FETs

Katherine Boucart, Mihai Adrian Ionescu, Walter Riess

In this letter, we propose a lateral asymmetric strain profile in a silicon nanowire or ultrathin silicon film as a key technology booster for the performance of all-silicon Tunnel FETs. We demonstrate by simulation that a Gaussian tensile-strain profile with a maximum placed at the source side of a nanowire Tunnel FET with a 50-nm channel length provides an optimized solution for a low-standby-power switch. This leads to the following: 1) ultralow I-off (more than three decades lower than in the case of a device on uniformly strained silicon); 2) boosting of I-on (more than one decade higher compared to a silicon reference); and 3) an average subthreshold swing S-avg of 48 mV/dec at room temperature. Furthermore, the inherent finite drain threshold voltage of the Tunnel FET, which could be a disadvantage for logic design with Tunnel FETs, is exponentially reduced with the strain-induced bandgap shrinkage at the source side.

Institute of Electrical and Electronics Engineers2009

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Functionalized 3D 7x20-array of vertically stacked SiNW FET for streptavidin sensing

Elizabeth Buitrago Godinez, Montserrat Fernandez-Bolanos Badia, Mihai Adrian Ionescu

A 3D, vertically stacked silicon nanowire (SiNW) field effect transistor (FET) featuring a high density array (7×20) of fully depleted channels has been successfully fabricated by a CMOS compatible process on silicon on insulator (SOI) and functionalized for streptavidin detection for the first time. The channels are surrounded by conformal high-κ gate dielectrics (HfO2), and their conductivity can be uniquely tuned by three gates; a backgate (BG) and two symmetrical Pt side gates (SG) through a liquid, offering unique sensitivity tuning with high gate coupling (SS=75 mV/dec, α'=SS60mV/dec/SSmeasured=0.8, with highest sensitivity=93-99%, obtained for I=1 0pA-10nA, in weak inversion) ever published. © 2013 IEEE.

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EPFL2015