Timing closureThe Timing closure in VLSI design and electronics engineering is the process by which a logic design of a clocked synchronous circuit consisting of primitive elements such as combinatorial logic gates (AND, OR, NOT, NAND, NOR, etc.) and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements. Unlike in a computer program where there is no explicit delay to perform a calculation, logic circuits have intrinsic and well defined delays to propagate inputs to outputs.
Comparison of EDA softwareThis page is a comparison of electronic design automation (EDA) software which is used today to design the near totality of electronic devices. Modern electronic devices are too complex to be designed without the help of a computer. Electronic devices may consist of integrated circuits (ICs), printed circuit boards (PCBs), field-programmable gate arrays (FPGAs) or a combination of them. Integrated circuits may consist of a combination of digital and analog circuits.
Physical design (electronics)In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called integrated circuit layout.
Gate arrayA gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a prefabricated chip with components that are later interconnected into logic devices (e.g. NAND gates, flip-flops, etc.) according to custom order by adding metal interconnect layers in the factory. It was popular during the upheaval in the semiconductor industry in the 1980s, and its usage declined by the end of the 1990s.
Design for testingDesign for testing or design for testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no manufacturing defects that could adversely affect the product's correct functioning. Tests are applied at several steps in the hardware manufacturing flow and, for certain products, may also be used for hardware maintenance in the customer's environment.
Application-specific integrated circuitvignette|Un ASIC. Un ASIC (acronyme de l'anglais application-specific integrated circuit, littéralement « circuit intégré propre à une application ») est un circuit intégré spécialisé. En général, il regroupe sur la même puce un ou sur mesure. thumb|Autre exemple de puce ASIC. L'intérêt de l'intégration est de réduire les coûts de production et d'augmenter la fiabilité. Avantage pour le maître d'œuvre : un contrôle total du produit et un coût de production réduit.
Field-programmable gate arrayA field-programmable gate array (FPGA) is an integrated circuit designed to be configured after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together.
Junction Field Effect TransistorUn transistor de type JFET (Junction Field Effect Transistor) est un transistor à effet de champ dont la grille est directement en contact avec le canal. On distingue les JFET avec un canal de type N, et ceux avec un canal de type P. Le JFET est né le lorsque William Shockley dévoile que son équipe du laboratoire Bell a mis au point un tout nouveau transistor à jonction.
Logic optimizationLogic optimization is a process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. This process is a part of a logic synthesis applied in digital electronics and integrated circuit design. Generally, the circuit is constrained to a minimum chip area meeting a predefined response delay. The goal of logic optimization of a given circuit is to obtain the smallest logic circuit that evaluates to the same values as the original one.
Architecture de processeurUne architecture externe de processeur ou architecture de jeu d'instructions (ISA, de l'anglais instruction set architecture), ou tout simplement architecture (de processeur), est la spécification fonctionnelle d'un processeur, du point de vue du programmeur en langage machine. L'architecture comprend notamment la donnée d'un jeu d'instructions, d'un ensemble de registres visibles par le programmeur, d'une organisation de la mémoire et des entrées sorties, des modalités d'un éventuel support multiprocesseur, etc.
