Low-Power Circuit and System Design for Epileptic Seizure Detection at High Spatiotemporal Resolution

Smart and miniaturized implantable microsystems with diagnostic and therapeutic capabilities are becoming increasingly important for patients suffering from neurological disorders such as epilepsy. Recent developments in microfabrication technology have provided new insights into seizure generation at an unprecedented spatial scale. Based on these findings, designing powerful acquisition systems capable of probing the wide-range spatiotemporal activities within the brain holds a great promise to improve the quality of life of epileptic patients. It is expected that future neural recording interfaces will integrate hundreds of acquisition channels at relatively high sampling rates, making it crucial to perform sophisticated signal conditioning tasks within the sensors. A small size of the implantable system is critical to minimize potential clinical issues associated with implantation. The total power consumption should be minimized to avoid heat generation inside the brain. Substantial improvements in neural implant safety and longevity are needed to translate existing multisite neural recording systems into technology suitable for long-term use in patients. As a major technological barrier, the high overall data rates of digitized neural signals collected by dense electrode arrays can drastically increase the power consumption of the wireless transmission module. Consequently, extensive system-level design improvement is needed to meet the requirements of the implantable device, while preserving the high-resolution monitoring capability. In this context, we target the exploration and development of novel methods and tools for more accurate monitoring of the electrical activity of the epileptic brain during seizures. A precise focus localization and accurate early seizure detection are two major goals. Low-power circuit and system design techniques for data acquisition, compression and seizure detection in multichannel cortical implants are presented. In this context, the first fully-integrated circuit that addresses the multichannel compressed-domain feature extraction is proposed. Circuit challenges and techniques to optimize the neural amplifier topology at the frontend of the signal acquisition chain, in terms of power consumption, die area and noise are discussed. Then, compressive sensing is utilized as the main data reduction method in the proposed system. The existing microelectronic implementations of compressive sensing are applied in a single-channel basis. Therefore, these topologies incur a high power consumption and large silicon area. To overcome these issues, a new multichannel measurement scheme and an appropriate recovery scheme are proposed, which encode the whole array into a single compressed data stream. This technique circumvents the need to place one analog-to-digital converter inside each channel, which results in a significant area saving. Taking benefit of the area-efficient implementation of compressive sensing, the number of recording units implantable on the cortex which satisfy the energy constraints of the system is scaled up by a factor equal to the compression ratio. Finally, a new feature extraction method applied on the compressed signal of several channels is proposed. The spatial evolution of the intracranial EEG signals recorded by the adjacent electrodes and the corresponding behaviour in the compressed domain are exploited for detecting seizure onset.