Accurate Power Analysis for Near-Vt RRAM-based FPGA

Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs. However, very limited works focused so far on studying the power characteristics of RRAM-based FPGAs. In this paper, we first analyze the power characteristics of RRAM-based multiplexer at circuit level and then use electrical simulations to study power consumption of RRAM-based FPGA architectures. Experimental results show that RRAM-based FPGAs achieve a Power-Delay Product reduced by 50% compared to SRAM-based FPGA at nominal voltage and 20% compared to near-Vt SRAM-based FPGA, respectively.

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin, Xifan Tang

Resistive Random Access Memory (RRAM)-based FPGAs are predicted to outperform conventional FPGAs architectures in area, delay and power over a wide range of voltage operations, allowing novel energy-quality trade-offs for reconfigurable computing. The opportunity lies in that RRAMs can realize the functionality of a Static Random Access Memory (SRAM) and a transmission-gate in a unique device. However, most of predictive analysis shown in the state-of-the-art are achieved by using analytical models. Unfortunately, while analytical models have been intensively refined for conventional FPGA architectures, their accuracy on RRAM-based FPGAs has not been carefully investigated. Consequently, misleading conclusions may be caused by using inaccurate analytical models. In this paper, we rely on electrical simulations and semi-custom design tools to perform detailed area and power comparison between SRAM-based and RRAM-based FPGAs. To enable accurate analysis, we develop a synthesizable Verilog generator for both SRAM-based and RRAM-based FPGAs and also enhance FPGASPICE to support most recent advanced RRAM-based circuits and FPGA architectures. The area analyses are based on fullchip layouts of SRAM-based and RRAM-based FPGAs, which are produced by a semi-custom design flow. We consider a full FPGA fabric, including core logic, configuring peripherals and I/Os, which is more realistic than analytical models. The power analysis are based on SPICE simulation results by considering the twenty largest MCNC benchmarks. Simulation results identify that the target RHRS of RRAM-based FPGAs should be at least 20M Ω to guarantee energy improvements over SRAM-based FPGAs. Experimental results present that at nominal working voltage, RRAM-based FPGAs can improve up to 8% in area, on average 22% in delay and on average 16% in power respectively, as compared to SRAM-based counterparts. Compared to SRAMbased FPGAs working at nominal voltage, near-Vt RRAM-based FPGAs can outperform close to 2 × in Energy-Delay Product without delay overhead. As a result, RRAM-based FPGAs are more capable of trading-off energy and quality than the SRAM-based counterparts.

2018

A Study on the Programming Structures for RRAM-based FPGA Architectures

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Gain Kim, Xifan Tang

Field Programmable Gate Arrays (FPGAs) can benefit non-volatility and high-performance by exploiting Resistive Random Access Memories (RRAMs). In RRAM-based FPGAs, the memories do not only replace the SRAMs and store configurations, but they can also replace the transmission gates and propagate datapath signals. The high-performance achievable by RRAM-based FPGAs comes from the fact that the on-resistance of the memory devices RmathLRS is smaller than the equivalent resistance of a transmission gate. Efficient programming structures for RRAMs should provide high current density with a small area footprint, to obtain a low Rmath. In this paper, we first examine the efficiency of the widely-used 2Transistor/1RRAM (2T1R) programming structure and identify four major limitations of the 2T1R structure. To overcome these limitations, we propose a 2Transmission-Gates/1RRAM (2TG1R) and a 4Transistor/1RRAM (4T1R) programming structures. We perform both theoretical analysis and electrical simulations on the evaluated programming structures. 4T1R programming structure is the best in terms of current density with 1.4 x and 1.1 x as compared to 2T1R and 2TG1R counterparts, respectively. We also investigate the effect of boosting the programming voltage Vmathprog of the programming structures. Experimental results show that boosting Vmathprog for all the programming structures improves driving current of the evaluated programming structures by 3 x and area efficiency by 1.7 x on average.

Ieee-Inst Electrical Electronics Engineers Inc2016

A High-Performance Low-Power Near-Vt RRAM-based FPGA

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang

The routing architecture, heavily using programmable switches, dominates the area, delay and power of Field Programmable Gate Arrays (FPGAs). Resistive Random Access Memories (RRAMs) enable high-performance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting the very low on-resistance state achievable by RRAMs, RRAM-based routing multiplexers can be used to significantly reduce the FPGA routing delays. In addition, RRAM-based routing architectures are less sensitive to supply voltage reductions and show promises in low-power FPGA designs. In this paper, we propose a near- Vt low-power RRAM-based FPGA where both delay and power reductions are achieved. Experimental results demonstrate that a near-Vt RRAM-based FPGA design leads to a 15% area shrink, a 10% delay reduction, and a 65% power improvement, compared to a conventional FPGA design for a given technology node. To achieve low on-resistance values, RRAMs typically require high programming currents. In other word, they need relatively large programming transistors, potentially resulting in area, delay and power inefficiencies. We also present a design methodology to properly size the programming transistors of RRAMs in order to further improve the area-efficiency. Experimental results show that a correct programming transistor sizing strategy contributes to further 18% area and 2% delay shrink, compared to the initial near-Vt RRAM-based FPGA.

2014

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin, Xifan Tang

2018