Publications associées à Precise error determination of approximated components in sequential circuits with model checking

Improving First-Order Threshold Implementations of SKINNY

Andrea Felice Caforio, Daniel Patrick Collins, Subhadeep Banik, Ognjen Glamocanin

Threshold Implementations have become a popular generic technique to construct circuits resilient against power analysis attacks.In this paper, we look to devise efficient threshold circuits for the lightweight block cipher family SKINNY. The only threshol ...

Springer, Cham2021

Digital Design with Implicit State Machines

Martin Odersky, Aleksandar Prokopec, Fengyun Liu

Claude Shannon, in his famous thesis (1938), revolutionized circuit design by showing that Boolean algebra subsumes all ad-hoc methods that are used in designing switching circuits, or combinational circuits as they are commonly known today. But what is ...

2020

End-to-End Industrial Study of Retiming

Giovanni De Micheli, Cunxi Yu, Maciej Jerzy Ciesielski

Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic with ...

IEEE2018

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter, Mattia Cacciotti

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e. critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal an ...

2018

Design and Applications of Approximate Circuits by Gate-Level Pruning

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

Energy-efficiency is a critical concern for many systems, ranging from Internet of things objects and mobile devices to high-performance computers. Moreover, after 40 years of prosperity, Moore's law is starting to show its economic and technical limits. N ...

Ieee-Inst Electrical Electronics Engineers Inc2017

OTA-C based high-speed analog processing for real-time fault location in electrical power networks

Maher Kayal, François Krummenacher, François Pierre Gaugaz

This paper explores the potential and limitations of analog integrated circuit techniques for the simulation of low-loss or lossless 1D or 2D transmission mediums. In this approach, a transmission line is mapped into a ladder consisting of N identical LC e ...

Springer Verlag2016

Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders

Alexios Konstantinos Balatsoukas Stimming

The goal of channel coding is to detect and correct errors that appear during the transmission of information. In the past few decades, channel coding has become an integral part of most communications standards as it improves the energy-efficiency of tran ...

EPFL2016

Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

Rafal Tomasz Dlugosz

This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced wi ...

Institute of Electrical and Electronics Engineers2016

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Precise error determination of approximated components in sequential circuits with model checking

Improving First-Order Threshold Implementations of SKINNY

Digital Design with Implicit State Machines

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

End-to-End Industrial Study of Retiming

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Design and Applications of Approximate Circuits by Gate-Level Pruning

Efficient processing and detection of balanced codes

OTA-C based high-speed analog processing for real-time fault location in electrical power networks

Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders

Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

Graph Chatbot

Chattez avec Graph Search

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders

OTA-C based high-speed analog processing for real-time fault location in electrical power networks

Design and Applications of Approximate Circuits by Gate-Level Pruning

Efficient processing and detection of balanced codes

Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

End-to-End Industrial Study of Retiming

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Digital Design with Implicit State Machines

Improving First-Order Threshold Implementations of SKINNY